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opt_expr: Fix X and CO outputs for $alu identity-mapping rules.

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This commit is contained in:
Marcelina Kościelnicka 2020-04-14 18:59:49 +02:00
parent 3c4758c60e
commit 2f8541a92e
2 changed files with 83 additions and 10 deletions
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17
passes/opt/opt_expr.cc
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@ -1135,9 +1135,24 @@ skip_fine_alu:
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
if (cell->type == ID($alu)) {
bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
bool is_signed = a_signed && b_signed;
RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI));
int y_width = GetSize(cell->getPort(ID::Y));
module->connect(cell->getPort(ID::X), RTLIL::Const(State::S0, y_width));
if (sig_ci == State::S1) {
/* sub, b is 0 */
RTLIL::SigSpec a = cell->getPort(ID::A);
a.extend_u0(y_width, is_signed);
module->connect(cell->getPort(ID::X), module->Not(NEW_ID, a));
module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width));
} else {
/* add */
RTLIL::SigSpec ab = cell->getPort(identity_wrt_a ? ID::A : ID::B);
ab.extend_u0(y_width, is_signed);
module->connect(cell->getPort(ID::X), ab);
module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S0, y_width));
}
cell->unsetPort(ID::BI);
cell->unsetPort(ID::CI);
cell->unsetPort(ID::X);

74
tests/opt/opt_expr_alu.ys
View file

@ -8,7 +8,7 @@ alumacc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
select -assert-none t:$pos t:* %D
design -reset
@ -20,7 +20,7 @@ EOT
alumacc
select -assert-count 1 t:$alu
select -assert-count none t:$alu t:* %D
select -assert-none t:$alu t:* %D
design -reset
@ -33,7 +33,7 @@ EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
select -assert-none t:$pos t:* %D
design -reset
@ -46,7 +46,7 @@ EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
select -assert-none t:$pos t:* %D
design -reset
@ -60,7 +60,8 @@ alumacc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
select -assert-count 1 t:$not
select -assert-none t:$pos t:$not %% t:* %D
design -reset
@ -76,7 +77,7 @@ design -load postopt
select -assert-count 1 t:$alu
select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
select -assert-count 1 t:$not
select -assert-count none t:$alu t:$not t:* %D %D
select -assert-none t:$alu t:$not t:* %D %D
design -reset
@ -93,7 +94,7 @@ dump
select -assert-count 2 t:$alu
select -assert-count 1 t:$alu r:Y_WIDTH=2 %i
select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
select -assert-count none t:$alu t:* %D
select -assert-none t:$alu t:* %D
design -reset
@ -108,4 +109,61 @@ equiv_opt -assert opt -fine
design -load postopt
select -assert-count 2 t:$alu
select -assert-count 2 t:$alu r:Y_WIDTH=3 %i
select -assert-count none t:$alu t:* %D
select -assert-none t:$alu t:* %D
design -reset
read_verilog -icells <<EOT
module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
$alu #(
.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
.A_SIGNED(0), .B_SIGNED(0),
) alu (
.A(a), .B(4'h0),
.BI(1'b0), .CI(1'b0),
.Y(y), .X(x), .CO(co),
);
endmodule
EOT
equiv_opt -assert opt
design -load postopt
select -assert-none t:$alu
design -reset
read_verilog -icells <<EOT
module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
$alu #(
.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
.A_SIGNED(0), .B_SIGNED(0),
) alu (
.A(a), .B(4'h0),
.BI(1'b1), .CI(1'b1),
.Y(y), .X(x), .CO(co),
);
endmodule
EOT
equiv_opt -assert opt
design -load postopt
select -assert-none t:$alu
design -reset
read_verilog -icells <<EOT
module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
$alu #(
.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
.A_SIGNED(0), .B_SIGNED(0),
) alu (
.A(4'h0), .B(a),
.BI(1'b0), .CI(1'b0),
.Y(y), .X(x), .CO(co),
);
endmodule
EOT
equiv_opt -assert opt
design -load postopt
select -assert-none t:$alu