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https://github.com/YosysHQ/yosys
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Merge 8405b3b723
into 63b3ce0c77
This commit is contained in:
commit
2f7cb990ef
38 changed files with 602 additions and 253 deletions
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@ -57,7 +57,7 @@ struct CutpointPass : public Pass {
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for (auto module : design->selected_modules())
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{
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if (design->selected_whole_module(module->name)) {
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if (module->is_selected_whole()) {
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log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
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module->new_connections(std::vector<RTLIL::SigSig>());
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for (auto cell : vector<Cell*>(module->cells()))
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@ -2887,7 +2887,7 @@ struct SimPass : public Pass {
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if (!top_mod)
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log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
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} else {
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auto mods = design->selected_whole_modules();
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auto mods = design->selected_unboxed_whole_modules();
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if (GetSize(mods) != 1)
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log_cmd_error("Only one top module must be selected.\n");
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top_mod = mods.front();
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@ -3016,7 +3016,7 @@ struct Fst2TbPass : public Pass {
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if (!top_mod)
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log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
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} else {
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auto mods = design->selected_whole_modules();
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auto mods = design->selected_unboxed_whole_modules();
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if (GetSize(mods) != 1)
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log_cmd_error("Only one top module must be selected.\n");
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top_mod = mods.front();
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