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Merge remote-tracking branch 'origin/master' into xaig_dff

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This commit is contained in:
Eddie Hung 2019-08-19 10:07:27 -07:00
commit 2f4e0a5388
92 changed files with 2221 additions and 1126 deletions
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28
passes/techmap/abc9.cc
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@ -576,11 +576,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Cell *cell = nullptr;
if (mapped_cell->type == ID($_NOT_)) {
RTLIL::SigBit a_bit = mapped_cell->getPort(ID(A));
RTLIL::SigBit y_bit = mapped_cell->getPort(ID(Y));
RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
if (!a_bit.wire) {
mapped_cell->setPort(ID(Y), module->addWire(NEW_ID));
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@ -608,7 +608,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort(ID(A))].push_back(cell);
bit2sinks[cell->getPort(ID::A)].push_back(cell);
cell_stats[ID($lut)]++;
bit_users[a_bit].insert(mapped_cell->name);
bit_drivers[y_bit].insert(mapped_cell->name);
@ -624,9 +624,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Cell *existing_cell = nullptr;
if (mapped_cell->type == ID($lut)) {
if (GetSize(mapped_cell->getPort(ID(A))) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID(A)).as_wire()->name));
SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID(Y)).as_wire()->name));
if (GetSize(mapped_cell->getPort(ID::A)) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
module->connect(my_y, my_a);
if (markgroups) mapped_cell->attributes[ID(abcgroup)] = map_autoidx;
log_abort();
@ -739,7 +739,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
#if 0
toposort.analyze_loops = true;
#endif
bool no_loops = toposort.sort();
bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
#if 0
unsigned i = 0;
for (auto &it : toposort.loops) {
@ -762,8 +762,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (it == not2drivers.end())
continue;
RTLIL::Cell *driver_lut = it->second;
RTLIL::SigBit a_bit = not_cell->getPort(ID(A));
RTLIL::SigBit y_bit = not_cell->getPort(ID(Y));
RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
RTLIL::Const driver_mask;
a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
@ -779,7 +779,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// Push downstream LUTs past inverter
for (auto sink_cell : jt->second) {
SigSpec A = sink_cell->getPort(ID(A));
SigSpec A = sink_cell->getPort(ID::A);
RTLIL::Const mask = sink_cell->getParam(ID(LUT));
int index = 0;
for (; index < GetSize(A); index++)
@ -793,7 +793,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
i += 1 << (index+1);
}
A[index] = y_bit;
sink_cell->setPort(ID(A), A);
sink_cell->setPort(ID::A, A);
sink_cell->setParam(ID(LUT), mask);
}
@ -809,10 +809,10 @@ clone_lut:
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
auto cell = module->addLut(NEW_ID,
driver_lut->getPort(ID(A)),
driver_lut->getPort(ID::A),
y_bit,
driver_mask);
for (auto &bit : cell->connections_.at(ID(A))) {
for (auto &bit : cell->connections_.at(ID::A)) {
bit.wire = module->wires_.at(remap_name(bit.wire->name));
bit2sinks[bit].push_back(cell);
}