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Merge pull request #1524 from pepijndevos/gowindffinit
Gowin: add and test DFF init values
This commit is contained in:
Clifford Wolf
GitHub
commit
2ec6d832dc
5 changed files with 569 additions and 112 deletions
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@ -34,11 +34,12 @@ proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFS
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select -assert-count 1 t:DFF
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select -assert-count 1 t:LUT2
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select -assert-count 4 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D
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select -assert-none t:DFF t:LUT2 t:IBUF t:OBUF %% t:* %D
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design -load read
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224
tests/arch/gowin/init.v
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224
tests/arch/gowin/init.v
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@ -0,0 +1,224 @@
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module myDFF (output reg Q, input CLK, D);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK)
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Q <= D;
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endmodule
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module myDFFE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (CE)
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Q <= D;
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end
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endmodule // DFFE (positive clock edge; clock enable)
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module myDFFS (output reg Q, input D, CLK, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFS (positive clock edge; synchronous set)
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module myDFFSE (output reg Q, input D, CLK, CE, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
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module myDFFR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFR (positive clock edge; synchronous reset)
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module myDFFRE (output reg Q, input D, CLK, CE, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
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module myDFFP (output reg Q, input D, CLK, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFP (positive clock edge; asynchronous preset)
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module myDFFPE (output reg Q, input D, CLK, CE, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
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module myDFFC (output reg Q, input D, CLK, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFC (positive clock edge; asynchronous clear)
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module myDFFCE (output reg Q, input D, CLK, CE, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
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module myDFFN (output reg Q, input CLK, D);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK)
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Q <= D;
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endmodule
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module myDFFNE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (CE)
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Q <= D;
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end
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endmodule // DFFNE (negative clock edge; clock enable)
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module myDFFNS (output reg Q, input D, CLK, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFNS (negative clock edge; synchronous set)
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module myDFFNSE (output reg Q, input D, CLK, CE, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
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module myDFFNR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFNR (negative clock edge; synchronous reset)
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module myDFFNRE (output reg Q, input D, CLK, CE, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
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module myDFFNP (output reg Q, input D, CLK, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFNP (negative clock edge; asynchronous preset)
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module myDFFNPE (output reg Q, input D, CLK, CE, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
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module myDFFNC (output reg Q, input D, CLK, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFNC (negative clock edge; asynchronous clear)
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module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
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74
tests/arch/gowin/init.ys
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74
tests/arch/gowin/init.ys
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@ -0,0 +1,74 @@
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read_verilog init.v
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read_verilog -lib +/gowin/cells_sim.v
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design -save read
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proc
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flatten
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synth_gowin -run coarse:
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# check if all init values are handled
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check -assert -noinit
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# check if every flop mapped correctly
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select -assert-count 1 t:DFF
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:DFFCE
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select -assert-count 1 t:DFFE
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select -assert-count 1 t:DFFN
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select -assert-count 1 t:DFFNC
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select -assert-count 1 t:DFFNCE
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select -assert-count 1 t:DFFNE
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select -assert-count 1 t:DFFNP
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select -assert-count 1 t:DFFNPE
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select -assert-count 1 t:DFFNR
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select -assert-count 1 t:DFFNRE
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select -assert-count 1 t:DFFNS
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select -assert-count 1 t:DFFNSE
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select -assert-count 1 t:DFFP
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select -assert-count 1 t:DFFPE
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select -assert-count 1 t:DFFR
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select -assert-count 1 t:DFFRE
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select -assert-count 1 t:DFFS
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select -assert-count 1 t:DFFSE
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delete
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design -load read
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# these should synth to a flop with reset
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chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE
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# async should give a warning
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# sync should synth to a mux
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chparam -set INIT 0 myDFF*S* myDFF*P*
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chparam -set INIT 1 myDFF*R* myDFF*C*
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proc
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flatten
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synth_gowin -run coarse:
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# check the flops mapped as expected
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select -assert-count 1 t:DFF
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:DFFCE
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select -assert-count 1 t:DFFE
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select -assert-count 1 t:DFFN
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select -assert-count 1 t:DFFNC
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select -assert-count 1 t:DFFNCE
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select -assert-count 1 t:DFFNE
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select -assert-count 1 t:DFFNP
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select -assert-count 1 t:DFFNPE
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select -assert-count 0 t:DFFNR
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select -assert-count 0 t:DFFNRE
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select -assert-count 2 t:DFFNS
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select -assert-count 2 t:DFFNSE
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select -assert-count 1 t:DFFP
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select -assert-count 1 t:DFFPE
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select -assert-count 0 t:DFFR
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select -assert-count 0 t:DFFRE
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select -assert-count 2 t:DFFS
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select -assert-count 2 t:DFFSE
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select -assert-count 12 t:LUT2
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# check the expected leftover init values
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# this would happen if your reset value is not the initial value
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# which would be weird
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select -assert-count 8 a:init
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