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Akash Levy 2025-11-06 06:44:35 -08:00
parent a225b7a721
commit 2ebed571b5
3 changed files with 1054 additions and 749 deletions
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26
tests/techmap/abc_state.ys.DISABLED
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@ -1,26 +0,0 @@
read_verilog <<EOT
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule
EOT
abc -g all
design -reset
read_verilog <<EOT
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule
EOT
techmap
abc -g AND
select -assert-count 0 t:$_OR_
select -assert-count 1 t:$_AND_