From 2eb1051cca5dc17e022364da7ab8d89ff0fa1cf8 Mon Sep 17 00:00:00 2001 From: Natalia Kokoromyti Date: Fri, 19 Dec 2025 12:35:22 -0800 Subject: [PATCH] fix splitlarge wide_op test --- tests/opt/splitlarge_wide_op.tcl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/opt/splitlarge_wide_op.tcl b/tests/opt/splitlarge_wide_op.tcl index af3f4a431..5ba73d121 100644 --- a/tests/opt/splitlarge_wide_op.tcl +++ b/tests/opt/splitlarge_wide_op.tcl @@ -56,12 +56,13 @@ for {set i 0} {$i < 8} {incr i} { log -header "[op_name $i]" log -push design -reset - read_verilog wide_op.v + read_verilog splitlarge_wide_op.v hierarchy -top wide_op chparam -set width 1024 -set op $i wide_op yosys proc simplemap - equiv_opt -post -assert splitlarge -max_width 128 +equiv_opt -assert splitlarge +yosys splitlarge yosys select -assert-none r:A_WIDTH>128 yosys select -assert-none r:B_WIDTH>128 yosys select -assert-count [predict_adder_count 1024 128 $i] r:A_WIDTH