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test: add failing test

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This commit is contained in:
Eddie Hung 2020-05-04 12:18:02 -07:00
parent 584780d776
commit 2e911bc806
1 changed files with 5 additions and 0 deletions
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5
tests/verilog/upto.ys Normal file
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@ -0,0 +1,5 @@
read_verilog <<EOT
module top(input [-128:-65] a);
endmodule
EOT
dump