mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-22 22:03:40 +00:00
Smallclean
This commit is contained in:
parent
26d9bdb17c
commit
2e8ee9a44d
1 changed files with 7 additions and 14 deletions
|
@ -136,10 +136,9 @@ struct MuxpackWorker
|
||||||
{
|
{
|
||||||
for (auto wire : module->wires())
|
for (auto wire : module->wires())
|
||||||
{
|
{
|
||||||
if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
|
if (wire->port_output || wire->get_bool_attribute(ID::keep))
|
||||||
for (auto bit : sigmap(wire))
|
for (auto bit : sigmap(wire))
|
||||||
sigbit_with_non_chain_users.insert(bit);
|
sigbit_with_non_chain_users.insert(bit);
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
for (auto cell : module->cells())
|
for (auto cell : module->cells())
|
||||||
|
@ -153,20 +152,18 @@ struct MuxpackWorker
|
||||||
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
|
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
|
||||||
|
|
||||||
if (!fanout_split) {
|
if (!fanout_split) {
|
||||||
if (sig_chain_next.count(a_sig)) {
|
if (sig_chain_next.count(a_sig))
|
||||||
for (auto a_bit : a_sig.bits())
|
for (auto a_bit : a_sig.bits())
|
||||||
sigbit_with_non_chain_users.insert(a_bit);
|
sigbit_with_non_chain_users.insert(a_bit);
|
||||||
}
|
|
||||||
else {
|
else {
|
||||||
sig_chain_next[a_sig] = cell;
|
sig_chain_next[a_sig] = cell;
|
||||||
candidate_cells.insert(cell);
|
candidate_cells.insert(cell);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!b_sig.empty()) {
|
if (!b_sig.empty()) {
|
||||||
if (sig_chain_next.count(b_sig)) {
|
if (sig_chain_next.count(b_sig))
|
||||||
for (auto b_bit : b_sig.bits())
|
for (auto b_bit : b_sig.bits())
|
||||||
sigbit_with_non_chain_users.insert(b_bit);
|
sigbit_with_non_chain_users.insert(b_bit);
|
||||||
}
|
|
||||||
else {
|
else {
|
||||||
sig_chain_next[b_sig] = cell;
|
sig_chain_next[b_sig] = cell;
|
||||||
candidate_cells.insert(cell);
|
candidate_cells.insert(cell);
|
||||||
|
@ -184,10 +181,9 @@ struct MuxpackWorker
|
||||||
}
|
}
|
||||||
|
|
||||||
for (auto conn : cell->connections())
|
for (auto conn : cell->connections())
|
||||||
if (cell->input(conn.first)) {
|
if (cell->input(conn.first))
|
||||||
for (auto bit : sigmap(conn.second))
|
for (auto bit : sigmap(conn.second))
|
||||||
sigbit_with_non_chain_users.insert(bit);
|
sigbit_with_non_chain_users.insert(bit);
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -200,9 +196,8 @@ struct MuxpackWorker
|
||||||
SigSpec a_sig = sigmap(cell->getPort(ID::A));
|
SigSpec a_sig = sigmap(cell->getPort(ID::A));
|
||||||
if (cell->type == ID($mux)) {
|
if (cell->type == ID($mux)) {
|
||||||
SigSpec b_sig = sigmap(cell->getPort(ID::B));
|
SigSpec b_sig = sigmap(cell->getPort(ID::B));
|
||||||
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1) {
|
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
|
||||||
goto start_cell;
|
goto start_cell;
|
||||||
}
|
|
||||||
|
|
||||||
if (!sig_chain_prev.count(a_sig))
|
if (!sig_chain_prev.count(a_sig))
|
||||||
a_sig = b_sig;
|
a_sig = b_sig;
|
||||||
|
@ -215,18 +210,16 @@ struct MuxpackWorker
|
||||||
else log_abort();
|
else log_abort();
|
||||||
|
|
||||||
for (auto bit : a_sig.bits())
|
for (auto bit : a_sig.bits())
|
||||||
if (sigbit_with_non_chain_users.count(bit)) {
|
if (sigbit_with_non_chain_users.count(bit))
|
||||||
goto start_cell;
|
goto start_cell;
|
||||||
}
|
|
||||||
|
|
||||||
{
|
{
|
||||||
Cell *prev_cell = sig_chain_prev.at(a_sig);
|
Cell *prev_cell = sig_chain_prev.at(a_sig);
|
||||||
log_assert(prev_cell);
|
log_assert(prev_cell);
|
||||||
SigSpec s_sig = sigmap(cell->getPort(ID::S));
|
SigSpec s_sig = sigmap(cell->getPort(ID::S));
|
||||||
s_sig.append(sigmap(prev_cell->getPort(ID::S)));
|
s_sig.append(sigmap(prev_cell->getPort(ID::S)));
|
||||||
if (!excl_db.query(s_sig) && !ignore_excl) {
|
if (!excl_db.query(s_sig) && !ignore_excl)
|
||||||
goto start_cell;
|
goto start_cell;
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
continue;
|
continue;
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue