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	tests: aiger test for wire->start_offset != 0
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							|  | @ -0,0 +1,36 @@ | ||||||
|  | read_verilog <<EOT | ||||||
|  | module top(input [31:-32] a, input [-65:-128] b, output [128:65] c); | ||||||
|  | assign c = a & b; | ||||||
|  | endmodule | ||||||
|  | EOT | ||||||
|  | select -assert-count 1 i:a | ||||||
|  | select -assert-count 1 i:b | ||||||
|  | select -assert-count 1 o:c | ||||||
|  | select -assert-count 3 x:* s:64 %i | ||||||
|  | design -save read | ||||||
|  | 
 | ||||||
|  | !rm -rf neg.out | ||||||
|  | !mkdir neg.out | ||||||
|  | simplemap | ||||||
|  | write_aiger -map neg.out/neg.map neg.out/neg.aig | ||||||
|  | 
 | ||||||
|  | design -reset | ||||||
|  | read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig | ||||||
|  | select -assert-count 1 i:a | ||||||
|  | select -assert-count 1 i:b | ||||||
|  | select -assert-count 1 o:c | ||||||
|  | select -assert-count 3 x:* s:64 %i | ||||||
|  | 
 | ||||||
|  | 
 | ||||||
|  | design -load read | ||||||
|  | !rm -rf neg.out | ||||||
|  | !mkdir neg.out | ||||||
|  | simplemap | ||||||
|  | write_xaiger -map neg.out/neg.map neg.out/neg.aig | ||||||
|  | 
 | ||||||
|  | design -reset | ||||||
|  | read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig | ||||||
|  | select -assert-count 1 i:a | ||||||
|  | select -assert-count 1 i:b | ||||||
|  | select -assert-count 1 o:c | ||||||
|  | select -assert-count 3 x:* s:64 %i | ||||||
|  | @ -52,3 +52,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter | ||||||
| sat -verify -prove-asserts -show-ports -seq 16 miter | sat -verify -prove-asserts -show-ports -seq 16 miter | ||||||
| " -l ${aig}.log | " -l ${aig}.log | ||||||
| done | done | ||||||
|  | 
 | ||||||
|  | for y in *.ys; do | ||||||
|  |     echo "Running $y." | ||||||
|  |     ../../yosys $y -ql ${y%.*}.log | ||||||
|  | done | ||||||
|  |  | ||||||
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