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tests: aiger test for wire->start_offset != 0

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Eddie Hung 2020-05-02 09:56:10 -07:00
parent a0afa1787e
commit 2e78daf1ca
2 changed files with 41 additions and 0 deletions
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@ -0,0 +1,36 @@
read_verilog <<EOT
module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
assign c = a & b;
endmodule
EOT
select -assert-count 1 i:a
select -assert-count 1 i:b
select -assert-count 1 o:c
select -assert-count 3 x:* s:64 %i
design -save read
!rm -rf neg.out
!mkdir neg.out
simplemap
write_aiger -map neg.out/neg.map neg.out/neg.aig
design -reset
read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
select -assert-count 1 i:a
select -assert-count 1 i:b
select -assert-count 1 o:c
select -assert-count 3 x:* s:64 %i
design -load read
!rm -rf neg.out
!mkdir neg.out
simplemap
write_xaiger -map neg.out/neg.map neg.out/neg.aig
design -reset
read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
select -assert-count 1 i:a
select -assert-count 1 i:b
select -assert-count 1 o:c
select -assert-count 3 x:* s:64 %i