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tests: add formalff -clk2ff to fpga fsm.ys

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This commit is contained in:
Emil J. Tywoniak 2026-02-06 23:16:21 +01:00
parent c27803cb9f
commit 2e6d112a2d
12 changed files with 13 additions and 0 deletions
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tests/arch/xilinx/fsm.ys
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@ -7,6 +7,7 @@ design -save orig
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
@ -23,6 +24,7 @@ design -load orig
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)