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tests: add formalff -clk2ff to fpga fsm.ys

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This commit is contained in:
Emil J. Tywoniak 2026-02-06 23:16:21 +01:00
parent c27803cb9f
commit 2e6d112a2d
12 changed files with 13 additions and 0 deletions
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1
tests/arch/anlogic/fsm.ys
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@ -5,6 +5,7 @@ flatten
equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

1
tests/arch/ecp5/fsm.ys
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@ -5,6 +5,7 @@ flatten
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
miter -equiv -make_assert -flatten gold gate miter
techmap -map +/dff2ff.v
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

1
tests/arch/efinix/fsm.ys
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@ -5,6 +5,7 @@ flatten
equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

1
tests/arch/fabulous/fsm.ys
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@ -6,6 +6,7 @@ flatten
equiv_opt -run :prove -map +/fabulous/prims.v synth_fabulous
async2sync
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
stat
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

1
tests/arch/gatemate/fsm.ys
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@ -6,6 +6,7 @@ flatten
equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad
async2sync
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
stat
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

1
tests/arch/gowin/fsm.ys
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@ -5,6 +5,7 @@ flatten
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
#design -load postopt

1
tests/arch/ice40/fsm.ys
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@ -4,6 +4,7 @@ proc
flatten
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
formalff -clk2ff
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

1
tests/arch/intel_alm/fsm.ys
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@ -6,6 +6,7 @@ flatten
equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf
async2sync
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

1
tests/arch/machxo2/fsm.ys
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@ -5,6 +5,7 @@ flatten
equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

1
tests/arch/nanoxplore/fsm.ys
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@ -6,6 +6,7 @@ flatten
equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad
async2sync
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

1
tests/arch/nexus/fsm.ys
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@ -5,6 +5,7 @@ flatten
equiv_opt -run :prove -map +/nexus/cells_sim.v synth_nexus
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

2
tests/arch/xilinx/fsm.ys
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@ -7,6 +7,7 @@ design -save orig
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
@ -23,6 +24,7 @@ design -load orig
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad
miter -equiv -make_assert -flatten gold gate miter
formalff -clk2ff
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)