mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Merge pull request #773 from whitequark/opt_lut_elim_fixes

Browse source 
opt_lut: elimination fixes
This commit is contained in:
Clifford Wolf 2019-01-02 15:45:29 +01:00 • committed by GitHub
commit 2e606b1802
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 31 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

39
passes/opt/opt_lut.cc
View file

@ -36,7 +36,7 @@ struct OptLutWorker
dict<RTLIL::Cell*, pool<RTLIL::Cell*>> luts_dlogics;
dict<RTLIL::Cell*, pool<int>> luts_dlogic_inputs;
int combined_count = 0;
int eliminated_count = 0, combined_count = 0;
bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
{
@ -189,8 +189,16 @@ struct OptLutWorker
log("\n");
log("Eliminating LUTs.\n");
for (auto lut : luts)
pool<RTLIL::Cell*> worklist = luts;
while (worklist.size())
{
if (limit == 0)
{
log("Limit reached.\n");
break;
}
auto lut = worklist.pop();
SigSpec lut_input = sigmap(lut->getPort("\\A"));
pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
@ -256,13 +264,24 @@ struct OptLutWorker
else
{
SigSpec lut_output = lut->getPort("\\Y");
for (auto &port : index.query_ports(lut_output))
{
if (port.cell != lut && luts.count(port.cell))
worklist.insert(port.cell);
}
module->connect(lut_output, value);
sigmap.add(lut_output, value);
module->remove(lut);
luts.erase(lut);
luts_arity.erase(lut);
luts_dlogics.erase(lut);
luts_dlogic_inputs.erase(lut);
eliminated_count++;
if (limit > 0)
limit--;
}
}
}
@ -270,7 +289,7 @@ struct OptLutWorker
log("\n");
log("Combining LUTs.\n");
pool<RTLIL::Cell*> worklist = luts;
worklist = luts;
while (worklist.size())
{
if (limit == 0)
@ -568,16 +587,20 @@ struct OptLutPass : public Pass {
}
extra_args(args, argidx, design);
int total_count = 0;
int eliminated_count = 0, combined_count = 0;
for (auto module : design->selected_modules())
{
OptLutWorker worker(dlogic, module, limit - total_count);
total_count += worker.combined_count;
OptLutWorker worker(dlogic, module, limit - eliminated_count - combined_count);
eliminated_count += worker.eliminated_count;
combined_count += worker.combined_count;
}
if (total_count)
if (eliminated_count)
design->scratchpad_set_bool("opt.did_something", true);
if (combined_count)
design->scratchpad_set_bool("opt.did_something", true);
log("\n");
log("Combined %d LUTs.\n", total_count);
log("Eliminated %d LUTs.\n", eliminated_count);
log("Combined %d LUTs.\n", combined_count);
}
} OptLutPass;