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verilog: ignore '&&&' when not in -specify mode

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This commit is contained in:
Eddie Hung 2020-02-13 13:06:13 -08:00
parent b523ecf2f4
commit 2e51dc1856
3 changed files with 12 additions and 5 deletions
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2
frontends/verilog/verilog_lexer.l
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@ -440,7 +440,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
}
"&&&" {
if (!specify_mode) REJECT;
if (!specify_mode) return TOK_IGNORED_SPECIFY_AND;
return TOK_SPECIFY_AND;
}