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Merge pull request #5419 from YosysHQ/micko/verific_fix_nocolumns

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verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
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Miodrag Milanović 2025-10-14 17:05:31 +02:00 • committed by GitHub
commit 2e3bfca294
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5 changed files with 42 additions and 4 deletions
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4
frontends/verific/verific.cc
View file

@ -168,7 +168,7 @@ string get_full_netlist_name(Netlist *nl)
std::string format_src_location(DesignObj *obj)
{
if (obj == nullptr || obj->Linefile() == nullptr)
if (obj == nullptr || !obj->Linefile())
return std::string();
#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
return stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
@ -1995,7 +1995,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (import_netlist_instance_cells(inst, inst_name))
continue;
if (inst->IsOperator() && !verific_sva_prims.count(inst->Type()))
log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name());
log_warning("%sUnsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", announce_src_location(inst), inst->View()->Owner()->Name());
} else {
if (import_netlist_instance_gates(inst, inst_name))
continue;

13
tests/verific/ext_ramnet_err.sv Normal file
View file

@ -0,0 +1,13 @@
module sub_rom (input clk, input [3:0] addr, output reg [7:0] data);
reg [7:0] mem [0:15];
always @(posedge clk)
data <= mem[addr];
endmodule
module top (input clk, input [3:0] addr, output [7:0] data, input [3:0] f_addr, input [7:0] f_data);
sub_rom u_sub_rom (clk, addr, data);
always @(posedge clk)
assume(u_sub_rom.mem[f_addr] == f_data);
endmodule

5
tests/verific/ext_ramnet_err.ys Normal file
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@ -0,0 +1,5 @@
logger -expect error "ext_ramnet_err.sv:[0-9]+\.[0-9]+-[0-9]+\.[0-9]+: Memory net '[^']+' missing, possibly no driver, use verific -flatten." 1
verific -sv ext_ramnet_err.sv
verific -import top
logger -check-expected
design -reset

15
tests/verific/import_warning_operator.vhd Normal file
View file

@ -0,0 +1,15 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port (
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(3 downto 0)
);
end top;
architecture Behavioral of top is
begin
y <= a nor b;
end Behavioral;

5
tests/verific/import_warning_operator.ys Normal file
View file

@ -0,0 +1,5 @@
logger -expect warning "import_warning_operator.vhd:[0-9]+.[0-9]+-[0-9]+.[0-9]+: Unsupported Verific operator: nor_4 \(fallback to gate level implementation provided by verific\)" 1
verific -vhdl import_warning_operator.vhd
verific -import top
logger -check-expected
design -reset