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synth_intel_alm: alternative synthesis for Intel FPGAs

By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
This commit is contained in:
Dan Ravensloft 2019-11-19 10:19:00 +00:00 committed by Marcelina Kościelnicka
parent 4c52691a58
commit 2e37e62e6b
29 changed files with 1662 additions and 1 deletions

View file

@ -0,0 +1,20 @@
bram __MISTRAL_MLAB
init 0 # TODO: Re-enable when I figure out how LUTRAM init works
abits 5
dbits 16 @D32x16
dbits 18 @D32x18
dbits 20 @D32x20
groups 2
ports 1 1
wrmode 1 0
# read enable
enable 1 0
transp 1 0
clocks 1 2
clkpol 1 1
endbram
match __MISTRAL_MLAB
min efficiency 5
make_outreg
endmatch