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synth_intel_alm: alternative synthesis for Intel FPGAs

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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
This commit is contained in:
Dan Ravensloft 2019-11-19 10:19:00 +00:00 • committed by Marcelina Kościelnicka
parent 4c52691a58
commit 2e37e62e6b
29 changed files with 1662 additions and 1 deletions
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56
techlibs/intel_alm/common/alm_map.v Normal file
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module \$lut (A, Y);
parameter WIDTH = 1;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
generate
if (LUT == 2'b00) begin
assign Y = 1'b0;
end
else if (LUT == 2'b01) begin
MISTRAL_NOT _TECHMAP_REPLACE_(
.A(A[0]), .Q(Y)
);
end
else if (LUT == 2'b10) begin
assign Y = A;
end
else if (LUT == 2'b11) begin
assign Y = 1'b1;
end
endgenerate
end else
if (WIDTH == 2) begin
MISTRAL_ALUT2 #(.LUT(LUT)) _TECHMAP_REPLACE_(
.A(A[0]), .B(A[1]), .Q(Y)
);
end else
if (WIDTH == 3) begin
MISTRAL_ALUT3 #(.LUT(LUT)) _TECHMAP_REPLACE_(
.A(A[0]), .B(A[1]), .C(A[2]), .Q(Y)
);
end else
if (WIDTH == 4) begin
MISTRAL_ALUT4 #(.LUT(LUT)) _TECHMAP_REPLACE_(
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .Q(Y)
);
end else
if (WIDTH == 5) begin
MISTRAL_ALUT5 #(.LUT(LUT)) _TECHMAP_REPLACE_ (
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .Q(Y)
);
end else
if (WIDTH == 6) begin
MISTRAL_ALUT6 #(.LUT(LUT)) _TECHMAP_REPLACE_ (
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .Q(Y)
);
end else begin
wire _TECHMAP_FAIL_ = 1'b1;
end
endgenerate
endmodule