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Add "-W' wire delay arg to abc9, use from synth_xilinx

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Eddie Hung 2019-06-11 17:10:47 -07:00
parent d26646051c
commit 2dffa4685b
3 changed files with 14 additions and 11 deletions
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5
frontends/verilog/verilog_lexer.l
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@ -311,11 +311,6 @@ supply1 { return TOK_SUPPLY1; }
return TOK_ID;
}
"$"(info|warning|error|fatal) {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_ELAB_TASK;
}
"$signed" { return TOK_TO_SIGNED; }
"$unsigned" { return TOK_TO_UNSIGNED; }