mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-25 19:36:21 +00:00
Code Activity

timinginfo: special-case $specify2 in signorm invariant

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-03-26 19:42:33 +01:00
parent 8ae1d758e2
commit 2dfb691f8b
2 changed files with 4 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/rtlil_bufnorm.cc
View file

@ -1058,7 +1058,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
{
bool is_input_port = false;
if (module->sig_norm_index != nullptr) {
if (module->sig_norm_index != nullptr && type != ID($specify2) && type != ID($specify3) && type != ID($specrule)) {
module->sig_norm_index->sigmap.apply(signal);
auto dir = port_dir(portname);