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Make splitfanout more robust

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This commit is contained in:
Akash Levy 2024-08-14 05:29:03 -07:00
parent 55782682de
commit 2deabdd640
1 changed files with 8 additions and 5 deletions
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13
passes/cmds/splitfanout.cc
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@ -98,7 +98,7 @@ struct SplitfanoutWorker
// Iterate over bit users and create a new cell for each one // Iterate over bit users and create a new cell for each one
log("Splitting %s cell %s/%s into %d copies based on fanout:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1); log("Splitting %s cell %s/%s into %d copies based on fanout:\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
int foi = 0; int foi = 0;
cell->setPort(outport, module->addWire(NEW_ID, GetSize(outsig))); cell->setPort(outport, module->addWire(NEW_ID, GetSize(outsig))); // disconnect the original cell (to be deleted)
for (auto user : bit_users) for (auto user : bit_users)
{ {
// Create a new cell // Create a new cell
@ -107,17 +107,20 @@ struct SplitfanoutWorker
// Connect the new cell to the user // Connect the new cell to the user
if (std::get<1>(user) == IdString()) { if (std::get<1>(user) == IdString()) {
Wire *old_wire = module->wire(std::get<0>(user)); IdString old_name = std::get<0>(user);
Wire *new_wire = module->addWire(NEW_ID, old_wire); IdString new_name = module->uniquify(old_name.str());
Wire *old_wire = module->wire(old_name);
Wire *new_wire = module->addWire(new_name, old_wire);
module->swap_names(old_wire, new_wire); module->swap_names(old_wire, new_wire);
old_wire->port_id = 0;
old_wire->port_input = false; old_wire->port_input = false;
old_wire->port_output = false; old_wire->port_output = false;
new_cell->setPort(outport, new_wire); new_cell->setPort(outport, new_wire);
} }
else { else {
Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig)); Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig));
module->cell(std::get<0>(user))->setPort(std::get<1>(user), new_wire); SigSpec sig = module->cell(std::get<0>(user))->getPort(std::get<1>(user));
sig.replace(std::get<2>(user), new_wire);
module->cell(std::get<0>(user))->setPort(std::get<1>(user), sig);
new_cell->setPort(outport, new_wire); new_cell->setPort(outport, new_wire);
} }