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https://github.com/YosysHQ/yosys
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sim: Add Yosys witness (.yw) cosimulation
This commit is contained in:
Jannis Harder
parent
1494cfff00
commit
2dd5652215
1 changed files with 194 additions and 3 deletions
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@ -23,6 +23,7 @@
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#include "kernel/mem.h"
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#include "kernel/fstdata.h"
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#include "kernel/ff.h"
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#include "kernel/yw.h"
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#include <ctime>
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@ -1603,6 +1604,194 @@ struct SimWorker : SimShared
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write_output_files();
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}
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struct FoundYWPath
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{
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SimInstance *instance;
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Wire *wire;
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IdString memid;
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int addr;
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};
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struct YwHierarchy {
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dict<IdPath, FoundYWPath> signal_paths;
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dict<IdPath, FoundYWPath> clock_paths;
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};
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YwHierarchy prepare_yw_hierarchy(const ReadWitness &yw)
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{
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pool<IdPath> paths;
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dict<IdPath, pool<IdString>> mem_paths;
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for (auto &signal : yw.signals)
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paths.insert(signal.path);
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for (auto &clock : yw.clocks) {
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if (paths.count(clock.path))
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log_warning("Witness path `%s` is present as witness signal and as clock, treating as clock and ignoring signal data.\n", clock.path.str().c_str());
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paths.insert(clock.path);
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}
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for (auto &path : paths)
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if (path.has_address())
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mem_paths[path.prefix()].insert(path.back());
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YwHierarchy hierarchy;
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witness_hierarchy(top->module, top, [&](IdPath const &path, WitnessHierarchyItem item, SimInstance *instance) {
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if (item.cell != nullptr)
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return instance->children.at(item.cell);
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if (item.wire != nullptr) {
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if (paths.count(path)) {
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if (debug)
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log("witness hierarchy: found wire %s\n", path.str().c_str());
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bool inserted = hierarchy.signal_paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second;
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if (!inserted)
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log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str());
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}
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} else if (item.mem) {
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auto it = mem_paths.find(path);
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if (it != mem_paths.end()) {
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if (debug)
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log("witness hierarchy: found mem %s\n", path.str().c_str());
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IdPath word_path = path;
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word_path.emplace_back();
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for (auto addr_part : it->second) {
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word_path.back() = addr_part;
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int addr;
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word_path.get_address(addr);
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if (addr < item.mem->start_offset || (addr - item.mem->start_offset) >= item.mem->size)
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continue;
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bool inserted = hierarchy.signal_paths.emplace(word_path, {instance, nullptr, item.mem->memid, addr}).second;
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if (!inserted)
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log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str());
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}
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}
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}
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return instance;
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});
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for (auto &path : paths)
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if (!hierarchy.signal_paths.count(path))
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log_warning("Yosys witness path `%s` was not found in this design, ignoring\n", path.str().c_str());
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for (auto &clock : yw.clocks) {
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auto found_path_it = hierarchy.signal_paths.find(clock.path);
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if (found_path_it == hierarchy.signal_paths.end())
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continue;
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hierarchy.clock_paths.insert(*found_path_it);
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hierarchy.signal_paths.erase(found_path_it);
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paths.insert(clock.path);
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}
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// TODO add checks and warnings for witness signals (toplevel inputs, $any*) not present in the witness file
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return hierarchy;
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}
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void set_yw_state(const ReadWitness &yw, const YwHierarchy &hierarchy, int t)
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{
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log_assert(t >= 0 && t < GetSize(yw.steps));
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for (auto &signal : yw.signals) {
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if (signal.init_only && t >= 1)
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continue;
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auto found_path_it = hierarchy.signal_paths.find(signal.path);
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if (found_path_it == hierarchy.signal_paths.end())
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continue;
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auto &found_path = found_path_it->second;
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Const value = yw.get_bits(t, signal.bits_offset, signal.width);
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if (debug)
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log("yw: set %s to %s\n", signal.path.str().c_str(), log_const(value));
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if (found_path.wire != nullptr) {
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found_path.instance->set_state(
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SigChunk(found_path.wire, signal.offset, signal.width),
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value);
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} else if (!found_path.memid.empty()) {
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found_path.instance->register_memory_addr(found_path.memid, found_path.addr);
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found_path.instance->set_memory_state(
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found_path.memid, found_path.addr,
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value);
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}
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}
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}
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void set_yw_clocks(const ReadWitness &yw, const YwHierarchy &hierarchy, bool active_edge)
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{
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for (auto &clock : yw.clocks) {
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if (clock.is_negedge == clock.is_posedge)
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continue;
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auto found_path_it = hierarchy.clock_paths.find(clock.path);
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if (found_path_it == hierarchy.clock_paths.end())
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continue;
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auto &found_path = found_path_it->second;
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if (found_path.wire != nullptr) {
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found_path.instance->set_state(
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SigChunk(found_path.wire, clock.offset, 1),
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active_edge == clock.is_posedge ? State::S1 : State::S0);
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}
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}
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}
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void run_cosim_yw_witness(Module *topmod)
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{
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if (!clock.empty())
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log_cmd_error("The -clock option is not required nor supported when reading a Yosys witness file.\n");
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if (!reset.empty())
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log_cmd_error("The -reset option is not required nor supported when reading a Yosys witness file.\n");
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if (multiclock)
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log_warning("The -multiclock option is not required and ignored when reading a Yosys witness file.\n");
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ReadWitness yw(sim_filename);
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top = new SimInstance(this, scope, topmod);
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register_signals();
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YwHierarchy hierarchy = prepare_yw_hierarchy(yw);
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if (yw.steps.empty()) {
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log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename.c_str());
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} else {
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top->set_initstate_outputs(State::S1);
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set_yw_state(yw, hierarchy, 0);
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set_yw_clocks(yw, hierarchy, true);
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initialize_stable_past();
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register_output_step(0);
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if (!yw.clocks.empty()) {
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if (debug)
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log("Simulating non-active clock edge.\n");
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set_yw_clocks(yw, hierarchy, false);
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update(false);
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register_output_step(5);
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}
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top->set_initstate_outputs(State::S0);
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}
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for (int cycle = 1; cycle < GetSize(yw.steps); cycle++)
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{
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if (verbose)
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log("Simulating cycle %d.\n", cycle);
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set_yw_state(yw, hierarchy, cycle);
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set_yw_clocks(yw, hierarchy, true);
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update(true);
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register_output_step(10 * cycle);
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if (!yw.clocks.empty()) {
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if (debug)
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log("Simulating non-active clock edge.\n");
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set_yw_clocks(yw, hierarchy, false);
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update(false);
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register_output_step(5 + 10 * cycle);
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}
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}
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register_output_step(10*GetSize(yw.steps));
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write_output_files();
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}
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std::string define_signal(Wire *wire)
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{
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std::stringstream f;
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@ -2132,9 +2321,9 @@ struct SimPass : public Pass {
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log(" -w\n");
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log(" writeback mode: use final simulation state as new init state\n");
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log("\n");
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log(" -r\n");
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log(" read simulation results file\n");
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log(" File formats supported: FST, VCD, AIW and WIT\n");
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log(" -r <filename>\n");
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log(" read simulation or formal results file\n");
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log(" File formats supported: FST, VCD, AIW, WIT and .yw\n");
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log(" VCD support requires vcd2fst external tool to be present\n");
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log("\n");
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log(" -map <filename>\n");
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@ -2354,6 +2543,8 @@ struct SimPass : public Pass {
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worker.run_cosim_aiger_witness(top_mod);
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} else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".wit") == 0) {
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worker.run_cosim_btor2_witness(top_mod);
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} else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".yw") == 0) {
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worker.run_cosim_yw_witness(top_mod);
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} else {
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log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename.c_str());
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}
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