From 2d9fdf859c4893ae2048fc46f05713aacd41ff43 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 7 Jul 2026 14:49:40 +0200 Subject: [PATCH] Add slang information in README --- README.md | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 61062243b..7dc02522e 100644 --- a/README.md +++ b/README.md @@ -5,6 +5,9 @@ This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. +Yosys is using [sv-elab](https://github.com/povik/sv-elab) and [slang](https://github.com/MikePopoloski/slang) libraries to provide comprehensive SystemVerilog support. +It supports an (informally defined) synthesizable subset of SystemVerilog in version IEEE 1800-2017 or IEEE 1800-2023. + Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ @@ -67,13 +70,9 @@ on Read the Docs. When cloning Yosys, some required libraries are included as git submodules. Make sure to call e.g. - $ git clone --recurse-submodules https://github.com/YosysHQ/yosys.git - -or - $ git clone https://github.com/YosysHQ/yosys.git $ cd yosys - $ git submodule update --init --recursive + $ git submodule update --init A C++ compiler with C++20 support is required as well as some standard tools such as GNU Flex, GNU Bison (>=3.8), CMake (>=3.28), Make (or other CMake