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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-09-09 06:51:28 -07:00 • committed by GitHub
commit 2d5c16b798
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4
passes/memory/memlib.cc
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@ -855,7 +855,9 @@ struct Parser {
PortVariant var;
var.options = portopts;
var.kind = pdef.kind;
if (pdef.kind != PortKind::Ar) {
if (pdef.kind == PortKind::Ar) {
var.clk_en = false;
} else {
const ClockDef *cdef = find_single_cap(pdef.clock, cram.options, portopts, "clock");
if (!cdef)
log_error("%s:%d: missing clock capability.\n", filename.c_str(), orig_line);