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Release version 0.67

This commit is contained in:
Miodrag Milanovic 2026-07-09 10:13:26 +02:00
parent 9c0291e81c
commit 2d1509d1bc
3 changed files with 32 additions and 3 deletions

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@ -2,8 +2,37 @@
List of major changes and improvements between releases
=======================================================
Yosys 0.66 .. Yosys 0.67-dev
Yosys 0.66 .. Yosys 0.67
--------------------------
* Various
- Project is now requiring CMake 3.28 or later as
build system.
- At least Clang-16 or GCC-13 are required, but we
recommend using later versions.
- Microsoft Visual Studio builds are now fully working
(including building ABC), but mingw-64 builds are
still recommended for Windows platform.
- For SystemVerilog support now using sv-elab,
built on top of slang library.
- FABulous techlib to removes all hardcoded mappings
and primitives, allowing them to be specified via
the options of "synth_fabulous".
- smtbmc: Latest bitwuzla is now supported.
* New commands and options
- Added "abc_ops_reintegrate" pass as replacement
for "abc9_ops -reintegrate".
- Added "check_mem" pass to check for memory problems
in the design.
- Added "-strategy", "-final" and "-no-fma" options to
"arith_tree" pass.
- Added "-ignore-unknown-cells" option to "equiv_opt".
- Added "-no-undriven-check" and "-undriven-warn" options
to "sim" pass.
- Added "-latches" option to synth passes able to
produce latches for control of latch inference.
- Added "-nolatches" to "check" pass.
- Added "-latches" to "proc" and "proc_dlatch" passes.
Yosys 0.65 .. Yosys 0.66
--------------------------

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set(YOSYS_VERSION_MAJOR 0)
set(YOSYS_VERSION_MINOR 66)
set(YOSYS_VERSION_MINOR 67)

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@ -6,7 +6,7 @@ import os
project = 'YosysHQ Yosys'
author = 'YosysHQ GmbH'
copyright ='2026 YosysHQ GmbH'
yosys_ver = "0.66"
yosys_ver = "0.67"
# select HTML theme
html_theme = 'furo-ys'