mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	Temporarily derive blackbox modules in hierarchy to evaluate port widths
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
		
							parent
							
								
									9804ebedbf
								
							
						
					
					
						commit
						2d140a44eb
					
				
					 1 changed files with 14 additions and 1 deletions
				
			
		|  | @ -620,6 +620,8 @@ struct HierarchyPass : public Pass { | |||
| 			} | ||||
| 		} | ||||
| 
 | ||||
| 		std::set<Module*> blackbox_derivatives; | ||||
| 
 | ||||
| 		for (auto module : design->modules()) | ||||
| 		for (auto cell : module->cells()) | ||||
| 		{ | ||||
|  | @ -628,9 +630,17 @@ struct HierarchyPass : public Pass { | |||
| 
 | ||||
| 			Module *m = design->module(cell->type); | ||||
| 
 | ||||
| 			if (m == nullptr || m->get_bool_attribute("\\blackbox")) | ||||
| 			if (m == nullptr) | ||||
| 				continue; | ||||
| 
 | ||||
| 			if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) { | ||||
| 				IdString new_m_name = m->derive(design, cell->parameters); | ||||
| 				if (new_m_name != m->name) { | ||||
| 					m = design->module(new_m_name); | ||||
| 					blackbox_derivatives.insert(m); | ||||
| 				} | ||||
| 			} | ||||
| 
 | ||||
| 			for (auto &conn : cell->connections()) | ||||
| 			{ | ||||
| 				Wire *w = m->wire(conn.first); | ||||
|  | @ -673,6 +683,9 @@ struct HierarchyPass : public Pass { | |||
| 			} | ||||
| 		} | ||||
| 
 | ||||
| 		for (auto module : blackbox_derivatives) | ||||
| 			design->remove(module); | ||||
| 
 | ||||
| 		log_pop(); | ||||
| 	} | ||||
| } HierarchyPass; | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue