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Small naming fixes to remove sig_ prefix
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parent
0757e27683
commit
2d105fc2c3
2 changed files with 7 additions and 7 deletions
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@ -1014,12 +1014,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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RTLIL::SigBit a = sig_a[i];
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if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
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module->connect(sig_y[i], a);
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module->connect(sig_x[i], ci ? module->Not(NEW_ID2_SUFFIX("sig_x_inv"), a, false, cell->get_src_attribute()).as_bit() : a); // SILIMATE: Improve the naming
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module->connect(sig_x[i], ci ? module->Not(NEW_ID2_SUFFIX("x_inv"), a, false, cell->get_src_attribute()).as_bit() : a); // SILIMATE: Improve the naming
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module->connect(sig_co[i], ci ? State::S1 : State::S0);
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}
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else if (a == (ci ? State::S1 : State::S0)) {
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module->connect(sig_y[i], bi ? module->Not(NEW_ID2_SUFFIX("sig_y_inv"), b, false, cell->get_src_attribute()).as_bit() : b); // SILIMATE: Improve the naming
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module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID2_SUFFIX("sig_x_inv"), b, false, cell->get_src_attribute()).as_bit() : b); // SILIMATE: Improve the naming
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module->connect(sig_y[i], bi ? module->Not(NEW_ID2_SUFFIX("y_inv"), b, false, cell->get_src_attribute()).as_bit() : b); // SILIMATE: Improve the naming
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module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID2_SUFFIX("x_inv"), b, false, cell->get_src_attribute()).as_bit() : b); // SILIMATE: Improve the naming
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module->connect(sig_co[i], ci ? State::S1 : State::S0);
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}
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else
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@ -1436,7 +1436,7 @@ skip_fine_alu:
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/* sub, b is 0 */
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RTLIL::SigSpec a = cell->getPort(ID::A);
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a.extend_u0(y_width, is_signed);
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module->connect(cell->getPort(ID::X), module->Not(NEW_ID2_SUFFIX("sig_ci_inv"), a, false, cell->get_src_attribute())); // SILIMATE: Improve the naming
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module->connect(cell->getPort(ID::X), module->Not(NEW_ID2_SUFFIX("ci_inv"), a, false, cell->get_src_attribute())); // SILIMATE: Improve the naming
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module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width));
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} else {
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/* add */
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