replace space indent with tab indent

passes/pmgen/mchp_dsp_cascade.pmg

@@ -221,8 +221,6 @@ code
 		{
 			subpattern(tail);
 		}
-                
-
 	} else {
 		if (GetSize(chain) > GetSize(longest_chain))
 			longest_chain = chain;

techlibs/mchp/LSRAM_map.v

@@ -259,7 +259,6 @@ generate
 		assign PORT_R_RD_DATA[19:0] = B_read_data[19:0];
 		assign PORT_R_RD_DATA[39:20] = A_read_data[19:0];
 	end
-    
 endgenerate
 
 // port width
@@ -314,9 +313,7 @@ RAM1K20 #(
 	// Disable ECC for SDP
 	.ECC_EN(1'b0), 
 	.ECC_BYPASS(1'b1),
-
 	.BUSY_FB(1'b0)
-
 );
 
 

techlibs/mchp/cells_sim.v

@@ -644,7 +644,6 @@ module RAM1K18 (
 	input			B_DOUT_CLK,
 	input			B_DOUT_EN,
 	input			B_DOUT_SRST_N,
-
 	input			A_EN,
 	input			B_EN,
 	input			SII_LOCK,
@@ -840,7 +839,7 @@ module RAM64x12 (
 
 	input		W_CLK,
 	input [5:0]	W_ADDR,
-	input  [11:0]   W_DATA,
+	input [11:0]W_DATA,
 	input		W_EN,
 
 	input		BUSY_FB,

techlibs/mchp/tests/reduce/reduce.v

@@ -20,7 +20,7 @@ module reduce(
 	input [7:0] data,
 	output Y
 
-    );
+);
 
 
 assign Y = ^data;

techlibs/mchp/tests/reg_c/reg_c.v

@@ -101,22 +101,22 @@ end
 
 // sync reset C
 always@(posedge clk) begin
-    if (srst_C_N) begin
+if (srst_C_N) begin
 	reg_C = 5'b00000;
-    end else begin
+end else begin
 	reg_C = in_C;
-    end
+end
 end
 
 
 
 // sync reset P
 always@(posedge clk) begin
-    if (srst_P_N) begin
+if (srst_P_N) begin
 	out_P = 12'h000;
-    end else begin
+end else begin
 	out_P = reg_A * (reg_B + reg_D) + reg_C;
-    end
+end
 end
 
 endmodule

techlibs/mchp/tests/widemux/widemux.v

@@ -22,11 +22,11 @@ module widemux(
 	input S1,
 	output Y
 
-    );
+);
 
-    wire A, B;
+wire A, B;
 
-    always @ (*) begin 
+always @ (*) begin 
 		if (S0)begin
 		A = data[1];
 		B = data[3];
@@ -41,7 +41,7 @@ module widemux(
 		Y = B;
 	end
 
-    end
+end
 endmodule
 
 

techlibs/mchp/uSRAM.txt

@@ -50,7 +50,7 @@ ram block $__uSRAM_SR_ {
 
 	init any;
 	abits 6;
-    widths 12 per_port;
+widths 12 per_port;
 
 	port sw "W" {
 		clock posedge;