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replace space indent with tab indent

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Chun Lin Min 2024-07-02 13:47:18 -07:00
parent acddc36389
commit 2ced2752e9
31 changed files with 791 additions and 797 deletions
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20
techlibs/mchp/tests/Registers/Registers.v
View file

@ -17,21 +17,21 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module Registers(
input clk,
input en,
input rst,
input D,
output Q
input clk,
input en,
input rst,
input D,
output Q
);
parameter LOAD_DATA = 1;
// active low async reset
always @(posedge clk, negedge rst) begin
if (rst == 0) begin
Q <= LOAD_DATA;
end else if(en) begin
Q <= D;
end
if (rst == 0) begin
Q <= LOAD_DATA;
end else if(en) begin
Q <= D;
end
end

10
techlibs/mchp/tests/carryout/carryout.v
View file

@ -25,10 +25,10 @@ input [n:0] a;
input [n:0] b;
input [n-1:0] c;
always @(a,b,c)
begin
{cout,out} = a * b + c;
end
always @(a,b,c)
begin
{cout,out} = a * b + c;
end
endmodule

12
techlibs/mchp/tests/cascade/cascade.v
View file

@ -17,13 +17,13 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module cascade(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output signed [11:0] out_P,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output signed [11:0] out_P,
input signed [4:0] casA,
input signed [4:0] casB
input signed [4:0] casA,
input signed [4:0] casB
);

20
techlibs/mchp/tests/dff_opt/dff_opt.v
View file

@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module dff_opt(
input clk,
input [1:0] D_comb,
input [1:0] EN_comb,
input [1:0] RST_comb,
output bar
input clk,
input [1:0] D_comb,
input [1:0] EN_comb,
input [1:0] RST_comb,
output bar
);
// DFF with enable that can be merged into D
@ -32,11 +32,11 @@ assign bar = foo;
// sync reset
always@(posedge clk) begin
if (&RST_comb) begin
foo <= 0;
end else begin
foo <= &D_comb;
end
if (&RST_comb) begin
foo <= 0;
end else begin
foo <= &D_comb;
end
end
endmodule

10
techlibs/mchp/tests/full_dsp/full_dsp.v
View file

@ -16,12 +16,12 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module full_dsp(
input signed[5:0] in_A,
input signed [4:0] in_B,
input signed [11:0] in_C,
input signed [4:0] in_D,
input signed[5:0] in_A,
input signed [4:0] in_B,
input signed [11:0] in_C,
input signed [4:0] in_D,
output signed [12:0] out_Y
output signed [12:0] out_Y
);
assign out_Y = ((in_D + in_B)*in_A)+in_C;

6
techlibs/mchp/tests/large_mult/large_mult.v
View file

@ -17,9 +17,9 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module large_mult(
input signed [20:0] in1,
input signed [17:0] in2,
output signed [38:0] out1
input signed [20:0] in1,
input signed [17:0] in2,
output signed [38:0] out1
);
assign out1 = in1 * in2;
endmodule

26
techlibs/mchp/tests/mac/mac.v
View file

@ -17,27 +17,27 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module mac(
input clk,
input signed [4:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg signed [11:0] out_P,
input clk,
input signed [4:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg signed [11:0] out_P,
input srst_P,
input srst_P,
input signed [4:0] casA,
input signed [4:0] casB
input signed [4:0] casA,
input signed [4:0] casB
);
// sync reset P
always@(posedge clk) begin
if (~srst_P) begin
out_P <= 12'h000;
end else begin
out_P <= in_A * (in_B + in_D) + out_P;
end
if (~srst_P) begin
out_P <= 12'h000;
end else begin
out_P <= in_A * (in_B + in_D) + out_P;
end
end
endmodule

8
techlibs/mchp/tests/postAdd_mult/postAdd_mult.v
View file

@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module postAdd_mult(
input signed[17:0] in_A,
input signed [17:0] in_B,
input signed [17:0] in_C,
input signed[17:0] in_A,
input signed [17:0] in_B,
input signed [17:0] in_C,
output signed [35:0] out_Y
output signed [35:0] out_Y
);
assign out_Y = (in_B*in_A)+in_C;

12
techlibs/mchp/tests/post_adder/post_adder.v
View file

@ -17,12 +17,12 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module post_adder(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input signed [11:0] in_C,
output [12:0] out_Y
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input signed [11:0] in_C,
output [12:0] out_Y
);
assign out_Y = (in_D + in_B) * in_A + in_C;

10
techlibs/mchp/tests/pre_adder_dsp/pre_adder_dsp.v
View file

@ -17,11 +17,11 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module pre_adder_dsp(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output [11:0] out_Y
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output [11:0] out_Y
);
assign out_Y = in_A * (in_B + in_D);

10
techlibs/mchp/tests/ram_SDP/ram_SDP.v
View file

@ -28,11 +28,11 @@ output reg [d_width-1:0] q;
reg [d_width-1:0] mem [mem_depth-1:0];
always @(posedge clk) begin
if (we) begin
mem[waddr] <= data;
end else begin
q <= mem[waddr];
end
if (we) begin
mem[waddr] <= data;
end else begin
q <= mem[waddr];
end
end
endmodule

10
techlibs/mchp/tests/ram_TDP/ram_TDP.v
View file

@ -27,11 +27,11 @@ reg [addr_width - 1 : 0] addra_reg, addrb_reg;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
always @ (posedge clka)
begin
addra_reg <= addra;
if(wea)
mem[addra] <= dataina;
end
begin
addra_reg <= addra;
if(wea)
mem[addra] <= dataina;
end
always @ (posedge clkb)
begin

6
techlibs/mchp/tests/reduce/reduce.v
View file

@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module reduce(
input [7:0] data,
output Y
input [7:0] data,
output Y
);
);
assign Y = ^data;

96
techlibs/mchp/tests/reg_c/reg_c.v
View file

@ -17,34 +17,34 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module reg_c(
input clk,
input clk,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input arst_D,
// active low
input arst_D,
input srst_C,
input arst_C,
input srst_C,
input arst_C,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_C,
input signed [4:0] in_D,
output reg [11:0] out_P
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_C,
input signed [4:0] in_D,
output reg [11:0] out_P
);
@ -69,54 +69,54 @@ reg signed [4:0] reg_D;
// sync reset A
always@(posedge clk) begin
// if (~srst_A_N) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
// if (~srst_A_N) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
end
// sync reset B
always@(posedge clk) begin
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
end
// async reset D
always@(posedge clk, negedge arst_D) begin
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
end
// sync reset C
always@(posedge clk) begin
if (srst_C_N) begin
reg_C = 5'b00000;
end else begin
reg_C = in_C;
end
if (srst_C_N) begin
reg_C = 5'b00000;
end else begin
reg_C = in_C;
end
end
// sync reset P
always@(posedge clk) begin
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D) + reg_C;
end
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D) + reg_C;
end
end
endmodule

76
techlibs/mchp/tests/reg_test/reg_test.v
View file

@ -17,28 +17,28 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module reg_test(
input clk,
input clk,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input arst_D,
// active low
input arst_D,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg [11:0] out_P
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg [11:0] out_P
);
@ -60,38 +60,38 @@ reg signed [4:0] reg_D;
// sync reset A
always@(posedge clk) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
end
// sync reset B
always@(posedge clk) begin
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
end
// async reset D
always@(posedge clk, negedge arst_D) begin
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
end
// sync reset P
always@(posedge clk) begin
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D);
end
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D);
end
end
endmodule

8
techlibs/mchp/tests/signed_mult/signed_mult.v
View file

@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module signed_mult(
input signed [17:0] in_A,
input signed [17:0] in_B,
output signed [35:0] out_Y
input signed [17:0] in_A,
input signed [17:0] in_B,
output signed [35:0] out_Y
);
assign out_Y = in_A * in_B;

6
techlibs/mchp/tests/simple_ram/simple_ram.v
View file

@ -29,9 +29,9 @@ reg [19:0] mem [0:1023] ;
assign dout = mem[addr_reg];
always@(posedge clk) begin
addr_reg <= addr;
if(wr)
mem[addr]<= din;
addr_reg <= addr;
if(wr)
mem[addr]<= din;
end
endmodule

8
techlibs/mchp/tests/unsigned_mult/unsigned_mult.v
View file

@ -17,10 +17,10 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module unsigned_mult(
input [10:0] in_A,
input signed [10:0] in_B,
output [21:0] out_Y
input [10:0] in_A,
input signed [10:0] in_B,
output [21:0] out_Y
);
assign out_Y = in_A * in_B;

4
techlibs/mchp/tests/uram_ar/uram_ar.v
View file

@ -30,8 +30,8 @@ reg [d_width-1:0] mem [mem_depth-1:0];
assign q = mem[waddr];
always @(posedge clk) begin
if (we)
mem[waddr] <= data;
if (we)
mem[waddr] <= data;
end

4
techlibs/mchp/tests/uram_sr/uram_sr.v
View file

@ -26,7 +26,7 @@ reg [5:0] raddr_reg;
reg [11:0] mem [0:63];
assign dout = mem[raddr_reg];
always@(posedge clk) begin
raddr_reg <= raddr; if(wr)
mem[waddr]<= din;
raddr_reg <= raddr; if(wr)
mem[waddr]<= din;
end
endmodule

40
techlibs/mchp/tests/widemux/widemux.v
View file

@ -17,31 +17,31 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module widemux(
input [3:0] data,
input S0,
input S1,
output Y
input [3:0] data,
input S0,
input S1,
output Y
);
);
wire A, B;
wire A, B;
always @ (*) begin
if (S0)begin
A = data[1];
B = data[3];
end else begin
A = data[0];
B = data[2];
end
always @ (*) begin
if (S0)begin
A = data[1];
B = data[3];
end else begin
A = data[0];
B = data[2];
end
if (S1)begin
Y = A;
end else begin
Y = B;
end
if (S1)begin
Y = A;
end else begin
Y = B;
end
end
end
endmodule