mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 09:05:32 +00:00
replace space indent with tab indent
This commit is contained in:
Chun Lin Min
parent
acddc36389
commit
2ced2752e9
31 changed files with 791 additions and 797 deletions
|
|
@ -56,7 +56,7 @@ udata <Cell*> dff
|
|||
// and (b) uses the 'C' port
|
||||
match dsp
|
||||
select dsp->type.in(\MACC_PA)
|
||||
select port(dsp, \C_BYPASS, SigSpec()).is_fully_ones()
|
||||
select port(dsp, \C_BYPASS, SigSpec()).is_fully_ones()
|
||||
select nusers(port(dsp, \C, SigSpec())) > 1
|
||||
endmatch
|
||||
|
||||
|
|
@ -76,14 +76,14 @@ code sigC sigP clock
|
|||
|
||||
SigSpec P = port(dsp, \P);
|
||||
|
||||
// Only care about those bits that are used
|
||||
int i;
|
||||
for (i = GetSize(P)-1; i >= 0; i--)
|
||||
if (nusers(P[i]) > 1)
|
||||
break;
|
||||
i++;
|
||||
log_assert(nusers(P.extract_end(i)) <= 1);
|
||||
sigP = P.extract(0, i);
|
||||
// Only care about those bits that are used
|
||||
int i;
|
||||
for (i = GetSize(P)-1; i >= 0; i--)
|
||||
if (nusers(P[i]) > 1)
|
||||
break;
|
||||
i++;
|
||||
log_assert(nusers(P.extract_end(i)) <= 1);
|
||||
sigP = P.extract(0, i);
|
||||
|
||||
clock = port(dsp, \CLK, SigBit());
|
||||
endcode
|
||||
|
|
@ -150,20 +150,20 @@ match ff
|
|||
endmatch
|
||||
|
||||
code argQ
|
||||
// Check that reset value, if present, is fully 0.
|
||||
// Check that reset value, if present, is fully 0.
|
||||
bool noResetFlop = ff->type.in($dff, $dffe);
|
||||
bool srstZero = ff->type.in($sdff, $sdffe) && param(ff, \SRST_VALUE).is_fully_zero();
|
||||
bool arstZero = ff->type.in($adff, $adffe) && param(ff, \ARST_VALUE).is_fully_zero();
|
||||
bool resetLegal = noResetFlop || srstZero || arstZero;
|
||||
if (resetLegal)
|
||||
{
|
||||
SigSpec Q = port(ff, \Q);
|
||||
dff = ff;
|
||||
dffclock = port(ff, \CLK);
|
||||
dffD = argQ;
|
||||
SigSpec D = port(ff, \D);
|
||||
argQ = Q;
|
||||
dffD.replace(argQ, D);
|
||||
}
|
||||
{
|
||||
SigSpec Q = port(ff, \Q);
|
||||
dff = ff;
|
||||
dffclock = port(ff, \CLK);
|
||||
dffD = argQ;
|
||||
SigSpec D = port(ff, \D);
|
||||
argQ = Q;
|
||||
dffD.replace(argQ, D);
|
||||
}
|
||||
|
||||
endcode
|
||||
|
|
|
|||
|
|
@ -60,16 +60,16 @@ endcode
|
|||
|
||||
// Helper function to remove unused bits
|
||||
code
|
||||
unextend = [](const SigSpec &sig) {
|
||||
int i;
|
||||
for (i = GetSize(sig)-1; i > 0; i--)
|
||||
if (sig[i] != sig[i-1])
|
||||
break;
|
||||
// Do not remove non-const sign bit
|
||||
if (sig[i].wire)
|
||||
++i;
|
||||
return sig.extract(0, i);
|
||||
};
|
||||
unextend = [](const SigSpec &sig) {
|
||||
int i;
|
||||
for (i = GetSize(sig)-1; i > 0; i--)
|
||||
if (sig[i] != sig[i-1])
|
||||
break;
|
||||
// Do not remove non-const sign bit
|
||||
if (sig[i].wire)
|
||||
++i;
|
||||
return sig.extract(0, i);
|
||||
};
|
||||
endcode
|
||||
|
||||
// (1) Starting from a DSP cell that
|
||||
|
|
@ -85,57 +85,57 @@ endmatch
|
|||
// height of a DSP column) with each DSP in each chunk being rewritten
|
||||
// to use [ABP]COUT -> [ABP]CIN cascading as appropriate
|
||||
code
|
||||
visited.clear();
|
||||
visited.insert(first);
|
||||
visited.clear();
|
||||
visited.insert(first);
|
||||
|
||||
longest_chain.clear();
|
||||
chain.emplace_back(first, -1);
|
||||
subpattern(tail);
|
||||
finally
|
||||
|
||||
// longest cascade chain has been found with DSP "first" being the head of the chain
|
||||
// do some post processing
|
||||
// longest cascade chain has been found with DSP "first" being the head of the chain
|
||||
// do some post processing
|
||||
|
||||
chain.pop_back();
|
||||
visited.clear();
|
||||
visited.clear();
|
||||
log_assert(chain.empty());
|
||||
|
||||
if (GetSize(longest_chain) > 1) {
|
||||
Cell *dsp = std::get<0>(longest_chain.front());
|
||||
|
||||
Cell *dsp_pcin;
|
||||
int SHIFT = -1;
|
||||
int SHIFT = -1;
|
||||
for (int i = 1; i < GetSize(longest_chain); i++) {
|
||||
log_assert(dsp->type.in(\MACC_PA));
|
||||
log_assert(dsp->type.in(\MACC_PA));
|
||||
|
||||
std::tie(dsp_pcin,SHIFT) = longest_chain[i];
|
||||
std::tie(dsp_pcin,SHIFT) = longest_chain[i];
|
||||
|
||||
// Chain length exceeds the maximum cascade length, must split it up
|
||||
// Chain length exceeds the maximum cascade length, must split it up
|
||||
if (i % MAX_DSP_CASCADE > 0) {
|
||||
Wire *cascade = module->addWire(NEW_ID, 48);
|
||||
Wire *cascade = module->addWire(NEW_ID, 48);
|
||||
|
||||
// zero port C and move wire to cascade
|
||||
dsp_pcin->setPort(ID(C), Const(0, 48));
|
||||
dsp_pcin->setPort(ID(CDIN), cascade);
|
||||
dsp->setPort(ID(CDOUT), cascade);
|
||||
// zero port C and move wire to cascade
|
||||
dsp_pcin->setPort(ID(C), Const(0, 48));
|
||||
dsp_pcin->setPort(ID(CDIN), cascade);
|
||||
dsp->setPort(ID(CDOUT), cascade);
|
||||
|
||||
// Configure wire to cascade the dsps
|
||||
add_siguser(cascade, dsp_pcin);
|
||||
add_siguser(cascade, dsp);
|
||||
// Configure wire to cascade the dsps
|
||||
add_siguser(cascade, dsp_pcin);
|
||||
add_siguser(cascade, dsp);
|
||||
|
||||
// configure mux to use cascade for signal E
|
||||
SigSpec cdin_fdbk_sel = port(dsp_pcin, \CDIN_FDBK_SEL, Const(0, 2));
|
||||
cdin_fdbk_sel[1] = State::S1;
|
||||
dsp_pcin->setPort(\CDIN_FDBK_SEL, cdin_fdbk_sel);
|
||||
// configure mux to use cascade for signal E
|
||||
SigSpec cdin_fdbk_sel = port(dsp_pcin, \CDIN_FDBK_SEL, Const(0, 2));
|
||||
cdin_fdbk_sel[1] = State::S1;
|
||||
dsp_pcin->setPort(\CDIN_FDBK_SEL, cdin_fdbk_sel);
|
||||
|
||||
// check if shifting is required for wide multiplier implmentation
|
||||
if (SHIFT == 17)
|
||||
{
|
||||
dsp_pcin->setPort(\ARSHFT17, State::S1);
|
||||
}
|
||||
|
||||
// check if shifting is required for wide multiplier implmentation
|
||||
if (SHIFT == 17)
|
||||
{
|
||||
dsp_pcin->setPort(\ARSHFT17, State::S1);
|
||||
}
|
||||
|
||||
|
||||
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
|
||||
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
|
||||
|
||||
} else {
|
||||
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
|
||||
|
|
@ -159,47 +159,47 @@ arg next
|
|||
// (b) 'C' port is driven by the 'P' output of the previous DSP cell
|
||||
// (c) has its 'PCIN' port unused
|
||||
match nextP
|
||||
// find candidates where nextP.C port is driven (maybe partially) by chain's tail DSP.P port
|
||||
// and with no registers in between (since cascade path cannot be pipelined)
|
||||
// find candidates where nextP.C port is driven (maybe partially) by chain's tail DSP.P port
|
||||
// and with no registers in between (since cascade path cannot be pipelined)
|
||||
|
||||
// reg C must not be used
|
||||
select port(nextP, \C_BYPASS, SigSpec()).is_fully_ones()
|
||||
// reg C must not be used
|
||||
select port(nextP, \C_BYPASS, SigSpec()).is_fully_ones()
|
||||
|
||||
// must be same DSP type
|
||||
select nextP->type.in(\MACC_PA)
|
||||
// must be same DSP type
|
||||
select nextP->type.in(\MACC_PA)
|
||||
|
||||
// port C should be driven by something
|
||||
// port C should be driven by something
|
||||
select nusers(port(nextP, \C, SigSpec())) > 1
|
||||
|
||||
// CIN must be unused
|
||||
// CIN must be unused
|
||||
select nusers(port(nextP, \PCIN, SigSpec())) == 0
|
||||
|
||||
// should not have internal feedback connection
|
||||
select port(nextP, \CDIN_FDBK_SEL, SigSpec()).is_fully_zero()
|
||||
|
||||
// SHIFT should be unused
|
||||
select port(nextP, \ARSHFT17_BYPASS).is_fully_ones()
|
||||
select port(nextP, \ARSHFT17).is_fully_zero()
|
||||
select nusers(port(nextP, \ARSHFT17, SigSpec())) == 0
|
||||
// should not have internal feedback connection
|
||||
select port(nextP, \CDIN_FDBK_SEL, SigSpec()).is_fully_zero()
|
||||
|
||||
// current DSP cell can be cascaded with the back of the cascade chain
|
||||
// SHIFT should be unused
|
||||
select port(nextP, \ARSHFT17_BYPASS).is_fully_ones()
|
||||
select port(nextP, \ARSHFT17).is_fully_zero()
|
||||
select nusers(port(nextP, \ARSHFT17, SigSpec())) == 0
|
||||
|
||||
// current DSP cell can be cascaded with the back of the cascade chain
|
||||
// index <SigBit> port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[17]
|
||||
filter port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[17]
|
||||
filter port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[0] || port(nextP, \C)[0] == port(std::get<0>(chain.back()), \P)[17]
|
||||
|
||||
// semioptional
|
||||
|
||||
optional
|
||||
optional
|
||||
endmatch
|
||||
|
||||
code next
|
||||
next = nextP;
|
||||
|
||||
// keep DSP type consistent in the chain
|
||||
// currently since we only have one type anyways, this line is always false
|
||||
// keep DSP type consistent in the chain
|
||||
// currently since we only have one type anyways, this line is always false
|
||||
if (next && next->type != first->type) reject;
|
||||
|
||||
// break infinite recursion when there's a combinational loop
|
||||
if (visited.count(next) > 0) reject;
|
||||
// break infinite recursion when there's a combinational loop
|
||||
if (visited.count(next) > 0) reject;
|
||||
|
||||
endcode
|
||||
|
||||
|
|
@ -207,32 +207,30 @@ endcode
|
|||
// longest possible chain
|
||||
code
|
||||
if (next) {
|
||||
SigSpec driver_sigP = port(std::get<0>(chain.back()), \P);
|
||||
int shift = 0;
|
||||
if (port(next, \C)[0] == port(std::get<0>(chain.back()), \P)[17]) shift = 17;
|
||||
SigSpec driver_sigP = port(std::get<0>(chain.back()), \P);
|
||||
int shift = 0;
|
||||
if (port(next, \C)[0] == port(std::get<0>(chain.back()), \P)[17]) shift = 17;
|
||||
|
||||
chain.emplace_back(next, shift);
|
||||
visited.insert(next);
|
||||
|
||||
visited.insert(next);
|
||||
|
||||
SigSpec sigC = unextend(port(next, \C));
|
||||
|
||||
// Make sure driverDSP.P === DSP.C
|
||||
if (GetSize(sigC) + shift <= GetSize(driver_sigP) && driver_sigP.extract(shift, GetSize(sigC)) == sigC)
|
||||
{
|
||||
subpattern(tail);
|
||||
}
|
||||
|
||||
|
||||
// Make sure driverDSP.P === DSP.C
|
||||
if (GetSize(sigC) + shift <= GetSize(driver_sigP) && driver_sigP.extract(shift, GetSize(sigC)) == sigC)
|
||||
{
|
||||
subpattern(tail);
|
||||
}
|
||||
} else {
|
||||
if (GetSize(chain) > GetSize(longest_chain))
|
||||
longest_chain = chain;
|
||||
}
|
||||
finally
|
||||
if (next)
|
||||
{
|
||||
visited.erase(next);
|
||||
chain.pop_back();
|
||||
}
|
||||
{
|
||||
visited.erase(next);
|
||||
chain.pop_back();
|
||||
}
|
||||
|
||||
|
||||
endcode
|
||||
Loading…
Add table
Add a link
Reference in a new issue