test suite

tests/arch/analogdevices/opt_lut_ins.ys

@@ -0,0 +1,26 @@
+read_rtlil << EOF
+
+module \top
+
+  wire width 4 input 1 \A
+
+  wire output 2 \O
+
+  cell \LUT4 $0
+    parameter \INIT 16'1111110011000000
+    connect \I0 \A [0]
+    connect \I1 \A [1]
+    connect \I2 \A [2]
+    connect \I3 \A [3]
+    connect \O \O
+  end
+end
+
+EOF
+
+read_verilog -lib +/analogdevices/cells_sim.v
+equiv_opt -assert -map +/analogdevices/cells_sim.v opt_lut_ins -tech xilinx
+
+design -load postopt
+
+select -assert-count 1 t:LUT3