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test suite

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Lofty 2025-09-24 20:56:27 +01:00
parent 04fd4d4601
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tests/arch/analogdevices/mul.ys Normal file
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read_verilog ../common/mul.v
hierarchy -top top
proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D