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test suite

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Lofty 2025-09-24 20:56:27 +01:00
parent 04fd4d4601
commit 2cdd97a8d4
38 changed files with 1282 additions and 161 deletions
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19
tests/arch/analogdevices/bug1605.ys Normal file
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read_verilog <<EOT
module top(inout io);
wire in;
wire t;
wire o;
IOBUF IOBUF(
.I(in),
.T(t),
.IO(io),
.O(o)
);
endmodule
EOT
synth_analogdevices
cd top
select -assert-count 1 t:IOBUF
select -assert-none t:* t:IOBUF %d