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test suite

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Lofty 2025-09-24 20:56:27 +01:00
parent 04fd4d4601
commit 2cdd97a8d4
38 changed files with 1282 additions and 161 deletions
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18
tests/arch/analogdevices/bug1480.ys Normal file
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read_verilog << EOF
module top(...);
input signed [17:0] A;
input signed [17:0] B;
output X;
output Y;
wire [35:0] P;
assign P = A * B;
assign X = P[0];
assign Y = P[35];
endmodule
EOF
synth_analogdevices