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Fix ignoring of simulation timings so that invalid module parameters cause syntax errors

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This commit is contained in:
Clifford Wolf 2017-09-26 01:52:59 +02:00
parent 143c0abd33
commit 2cc09161ff
2 changed files with 2 additions and 4 deletions
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2
frontends/verilog/verilog_parser.y
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@ -355,6 +355,8 @@ package_body_stmt:
localparam_decl;
non_opt_delay:
'#' TOK_ID { delete $2; } |
'#' TOK_CONSTVAL { delete $2; } |
'#' '(' expr ')' { delete $3; } |
'#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };