Renamed manual/FILES_* directories

manual/CHAPTER_StateOfTheArt/always01.v

@@ -0,0 +1,12 @@
+module uut_always01(clock, reset, c3, c2, c1, c0);
+
+input clock, reset;
+output c3, c2, c1, c0;
+reg [3:0] count;
+
+assign {c3, c2, c1, c0} = count;
+
+always @(posedge clock)
+	count <= reset ? 0 : count + 1;
+
+endmodule

manual/CHAPTER_StateOfTheArt/always01_pub.v

@@ -0,0 +1,14 @@
+module uut_always01(clock,
+		reset, count);
+
+input clock, reset;
+output [3:0] count;
+reg [3:0] count;
+
+always @(posedge clock)
+	count <= reset ?
+		0 : count + 1;
+
+
+
+endmodule

manual/CHAPTER_StateOfTheArt/always02.v

@@ -0,0 +1,15 @@
+module uut_always02(clock, reset, c3, c2, c1, c0);
+
+input clock, reset;
+output c3, c2, c1, c0;
+reg [3:0] count;
+
+assign {c3, c2, c1, c0} = count;
+
+always @(posedge clock) begin
+	count <= count + 1;
+	if (reset)
+		count <= 0;
+end
+
+endmodule

manual/CHAPTER_StateOfTheArt/always02_pub.v

@@ -0,0 +1,14 @@
+module uut_always02(clock,
+		reset, count);
+
+input clock, reset;
+output [3:0] count;
+reg [3:0] count;
+
+always @(posedge clock) begin
+	count <= count + 1;
+	if (reset)
+		count <= 0;
+end
+
+endmodule

manual/CHAPTER_StateOfTheArt/always03.v

@@ -0,0 +1,23 @@
+module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7,
+		out1, out2, out3);
+
+input clock, in1, in2, in3, in4, in5, in6, in7;
+output out1, out2, out3;
+reg out1, out2, out3;
+
+always @(posedge clock) begin
+	out1 = in1;
+	if (in2)
+		out1 = !out1;
+	out2 <= out1;
+	if (in3)
+		out2 <= out2;
+	if (in4)
+		if (in5)
+			out3 <= in6;
+		else
+			out3 <= in7;
+	out1 = out1 ^ out2;
+end
+
+endmodule

manual/CHAPTER_StateOfTheArt/arrays01.v

@@ -0,0 +1,16 @@
+module uut_arrays01(clock, we, addr, wr_data, rd_data);
+
+input clock, we;
+input [3:0] addr, wr_data;
+output [3:0] rd_data;
+reg [3:0] rd_data;
+
+reg [3:0] memory [15:0];
+
+always @(posedge clock) begin
+	if (we)
+		memory[addr] <= wr_data;
+	rd_data <= memory[addr];
+end
+
+endmodule

manual/CHAPTER_StateOfTheArt/cmp_tbdata.c

@@ -0,0 +1,67 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+
+int line = 0;
+char buffer1[1024];
+char buffer2[1024];
+
+void check(bool ok)
+{
+	if (ok)
+		return;
+	// fprintf(stderr, "Error in testbench output compare (line=%d):\n-%s\n+%s\n", line, buffer1, buffer2);
+	exit(1);
+}
+
+int main(int argc, char **argv)
+{
+	FILE *f1, *f2;
+	bool eof1, eof2;
+	int i;
+
+	check(argc == 3);
+
+	f1 = fopen(argv[1], "r");
+	f2 = fopen(argv[2], "r");
+
+	check(f1 && f2);
+
+	while (!feof(f1) && !feof(f2))
+	{
+		line++;
+		buffer1[0] = 0;
+		buffer2[0] = 0;
+
+		eof1 = fgets(buffer1, 1024, f1) == NULL;
+		eof2 = fgets(buffer2, 1024, f2) == NULL;
+
+		if (*buffer1 && buffer1[strlen(buffer1)-1] == '\n')
+			buffer1[strlen(buffer1)-1] = 0;
+
+		if (*buffer2 && buffer2[strlen(buffer2)-1] == '\n')
+			buffer2[strlen(buffer2)-1] = 0;
+
+		check(eof1 == eof2);
+
+		for (i = 0; buffer1[i] || buffer2[i]; i++)
+		{
+			check(buffer1[i] != 0 && buffer2[i] != 0);
+
+			// first argument is the reference. An 'z' or 'x'
+			// here means we don't care about the result.
+			if (buffer1[i] == 'z' || buffer1[i] == 'x')
+				continue;
+
+			check(buffer1[i] == buffer2[i]);
+		}
+	}
+
+	check(feof(f1) && feof(f2));
+
+	fclose(f1);
+	fclose(f2);
+	return 0;
+}
+

manual/CHAPTER_StateOfTheArt/forgen01.v

@@ -0,0 +1,20 @@
+module uut_forgen01(a, y);
+
+input [4:0] a;
+output y;
+
+integer i, j;
+reg [31:0] lut;
+
+initial begin
+	for (i = 0; i < 32; i = i+1) begin
+		lut[i] = i > 1;
+		for (j = 2; j*j <= i; j = j+1)
+			if (i % j == 0)
+				lut[i] = 0;
+	end
+end
+
+assign y = lut[a];
+
+endmodule

manual/CHAPTER_StateOfTheArt/forgen02.v

@@ -0,0 +1,30 @@
+module uut_forgen02(a, b, cin, y, cout);
+
+parameter WIDTH = 8;
+
+input [WIDTH-1:0] a, b;
+input cin;
+
+output [WIDTH-1:0] y;
+output cout;
+
+genvar i;
+wire [WIDTH-1:0] carry;
+
+generate
+	for (i = 0; i < WIDTH; i=i+1) begin:adder
+		wire [2:0] D;
+		assign D[1:0] = { a[i], b[i] };
+		if (i == 0) begin:chain
+			assign D[2] = cin;
+		end else begin:chain
+			assign D[2] = carry[i-1];
+		end
+		assign y[i] = ^D;
+		assign carry[i] = &D[1:0] | (^D[1:0] & D[2]);
+	end
+endgenerate
+
+assign cout = carry[WIDTH-1];
+
+endmodule

manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch

@@ -0,0 +1,20 @@
+--- ./elab_net.cc.orig	2012-10-27 22:11:05.345688820 +0200
++++ ./elab_net.cc	2012-10-27 22:12:23.398075860 +0200
+@@ -29,6 +29,7 @@
+ 
+ # include  <iostream>
+ # include  <cstring>
++# include  <memory>
+ 
+ /*
+  * This is a state flag that determines whether an elaborate_net must
+--- ./syn-rules.y.orig	2012-10-27 22:25:38.890020489 +0200
++++ ./syn-rules.y	2012-10-27 22:25:49.146071350 +0200
+@@ -25,6 +25,7 @@
+ # include "config.h"
+ 
+ # include  <iostream>
++# include  <stdio.h>
+ 
+ /*
+  * This file implements synthesis based on matching threads and

manual/CHAPTER_StateOfTheArt/mvsis-1.3.6-buildfixes.patch

@@ -0,0 +1,36 @@
+--- ./helpers/config.sub.orig	2012-10-27 22:09:04.429089223 +0200
++++ ./helpers/config.sub	2012-10-27 22:09:11.501124295 +0200
+@@ -158,6 +158,7 @@
+ 		| sparc | sparclet | sparclite | sparc64)
+ 		basic_machine=$basic_machine-unknown
+ 		;;
++	x86_64-pc) ;;
+ 	# We use `pc' rather than `unknown'
+ 	# because (1) that's what they normally are, and
+ 	# (2) the word "unknown" tends to confuse beginning users.
+--- ./src/base/ntki/ntkiFrames.c.orig	2012-10-27 22:09:26.961200963 +0200
++++ ./src/base/ntki/ntkiFrames.c	2012-10-27 22:09:32.901230409 +0200
+@@ -23,7 +23,7 @@
+ ////////////////////////////////////////////////////////////////////////
+ 
+ static void Ntk_NetworkAddFrame( Ntk_Network_t * pNetNew, Ntk_Network_t * pNet, int iFrame );
+-static void Ntk_NetworkReorderCiCo( Ntk_Network_t * pNet );
++// static void Ntk_NetworkReorderCiCo( Ntk_Network_t * pNet );
+ 
+ extern int  Ntk_NetworkVerifyVariables( Ntk_Network_t * pNet1, Ntk_Network_t * pNet2, int fVerbose );
+ 
+--- ./src/graph/wn/wnStrashBin.c.orig	2012-10-27 22:27:29.966571294 +0200
++++ ./src/graph/wn/wnStrashBin.c	2012-10-27 22:27:55.898699881 +0200
+@@ -76,8 +76,10 @@
+ //    assert( RetValue );
+ 
+     // clean the data of the nodes in the window
+-    Ntk_NetworkForEachNodeSpecial( pWnd->pNet, pNode )
+-        pNode->pCopy = (Ntk_Node_t *)pNode->pData = NULL;
++    Ntk_NetworkForEachNodeSpecial( pWnd->pNet, pNode ) {
++        pNode->pData = NULL;
++        pNode->pCopy = NULL;
++    }
+ 
+     // set the leaves
+     pgInputs = Sh_ManagerReadVars( pMan );

manual/CHAPTER_StateOfTheArt/simlib_icarus.v

@@ -0,0 +1,224 @@
+
+module cell0(Result0);
+output Result0;
+assign Result0 = 0;
+endmodule
+
+module cell1(Result0);
+output Result0;
+assign Result0 = 1;
+endmodule
+
+module ADD4(
+	DataA0, DataA1, DataA2, DataA3,
+	DataB0, DataB1, DataB2, DataB3,
+	Result0, Result1, Result2, Result3, Cout
+);
+input DataA0, DataA1, DataA2, DataA3;
+input DataB0, DataB1, DataB2, DataB3;
+output Result0, Result1, Result2, Result3, Cout;
+assign {Cout, Result3, Result2, Result1, Result0} = {DataA3, DataA2, DataA1, DataA0} + {DataB3, DataB2, DataB1, DataB0};
+endmodule
+
+module BUF(DATA, RESULT);
+input DATA;
+output RESULT;
+assign RESULT = DATA;
+endmodule
+
+module INV(DATA, RESULT);
+input DATA;
+output RESULT;
+assign RESULT = ~DATA;
+endmodule
+
+module fd4(
+	Clock,
+	Data0, Data1, Data2, Data3,
+	Q0, Q1, Q2, Q3
+);
+input Clock;
+input Data0, Data1, Data2, Data3;
+output reg Q0, Q1, Q2, Q3;
+always @(posedge Clock)
+	{Q0, Q1, Q2, Q3} <= {Data0, Data1, Data2, Data3};
+endmodule
+
+module fdce1(
+	Clock, Enable,
+	Data0,
+	Q0
+);
+input Clock, Enable;
+input Data0;
+output reg Q0;
+always @(posedge Clock)
+	if (Enable)
+		Q0 <= Data0;
+endmodule
+
+module fdce4(
+	Clock, Enable,
+	Data0, Data1, Data2, Data3,
+	Q0, Q1, Q2, Q3
+);
+input Clock, Enable;
+input Data0, Data1, Data2, Data3;
+output reg Q0, Q1, Q2, Q3;
+always @(posedge Clock)
+	if (Enable)
+		{Q0, Q1, Q2, Q3} <= {Data0, Data1, Data2, Data3};
+endmodule
+
+module mux4_1_2(
+	Sel0,
+	Data0x0, Data0x1, Data0x2, Data0x3,
+	Data1x0, Data1x1, Data1x2, Data1x3,
+	Result0, Result1, Result2, Result3
+);
+input Sel0;
+input Data0x0, Data0x1, Data0x2, Data0x3;
+input Data1x0, Data1x1, Data1x2, Data1x3;
+output Result0, Result1, Result2, Result3;
+assign {Result0, Result1, Result2, Result3} = Sel0 ? {Data1x0, Data1x1, Data1x2, Data1x3} : {Data0x0, Data0x1, Data0x2, Data0x3};
+endmodule
+
+module mux1_1_2(
+	Sel0,
+	Data0x0,
+	Data1x0,
+	Result0
+);
+input Sel0;
+input Data0x0;
+input Data1x0;
+output Result0;
+assign Result0 = Sel0 ? Data1x0 : Data0x0;
+endmodule
+
+module xor2(
+	DATA0X0,
+	DATA1X0,
+	RESULT0
+);
+input DATA0X0;
+input DATA1X0;
+output RESULT0;
+assign RESULT0 = DATA1X0 ^ DATA0X0;
+endmodule
+
+module fdce64(
+	Clock, Enable,
+	Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63,
+	Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63
+);
+input Clock, Enable;
+input Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63;
+output reg Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63;
+always @(posedge Clock)
+	if (Enable)
+		{ Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63 } <= { Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63 };
+endmodule
+
+module mux4_4_16(
+	Sel0, Sel1, Sel2, Sel3,
+	Result0, Result1, Result2, Result3,
+	Data0x0, Data0x1, Data0x2, Data0x3,
+	Data1x0, Data1x1, Data1x2, Data1x3,
+	Data2x0, Data2x1, Data2x2, Data2x3,
+	Data3x0, Data3x1, Data3x2, Data3x3,
+	Data4x0, Data4x1, Data4x2, Data4x3,
+	Data5x0, Data5x1, Data5x2, Data5x3,
+	Data6x0, Data6x1, Data6x2, Data6x3,
+	Data7x0, Data7x1, Data7x2, Data7x3,
+	Data8x0, Data8x1, Data8x2, Data8x3,
+	Data9x0, Data9x1, Data9x2, Data9x3,
+	Data10x0, Data10x1, Data10x2, Data10x3,
+	Data11x0, Data11x1, Data11x2, Data11x3,
+	Data12x0, Data12x1, Data12x2, Data12x3,
+	Data13x0, Data13x1, Data13x2, Data13x3,
+	Data14x0, Data14x1, Data14x2, Data14x3,
+	Data15x0, Data15x1, Data15x2, Data15x3
+);
+input Sel0, Sel1, Sel2, Sel3;
+output Result0, Result1, Result2, Result3;
+input Data0x0, Data0x1, Data0x2, Data0x3;
+input Data1x0, Data1x1, Data1x2, Data1x3;
+input Data2x0, Data2x1, Data2x2, Data2x3;
+input Data3x0, Data3x1, Data3x2, Data3x3;
+input Data4x0, Data4x1, Data4x2, Data4x3;
+input Data5x0, Data5x1, Data5x2, Data5x3;
+input Data6x0, Data6x1, Data6x2, Data6x3;
+input Data7x0, Data7x1, Data7x2, Data7x3;
+input Data8x0, Data8x1, Data8x2, Data8x3;
+input Data9x0, Data9x1, Data9x2, Data9x3;
+input Data10x0, Data10x1, Data10x2, Data10x3;
+input Data11x0, Data11x1, Data11x2, Data11x3;
+input Data12x0, Data12x1, Data12x2, Data12x3;
+input Data13x0, Data13x1, Data13x2, Data13x3;
+input Data14x0, Data14x1, Data14x2, Data14x3;
+input Data15x0, Data15x1, Data15x2, Data15x3;
+assign {Result0, Result1, Result2, Result3} =
+	{Sel3, Sel2, Sel1, Sel0} == 0 ? { Data0x0, Data0x1, Data0x2, Data0x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 1 ? { Data1x0, Data1x1, Data1x2, Data1x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 2 ? { Data2x0, Data2x1, Data2x2, Data2x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 3 ? { Data3x0, Data3x1, Data3x2, Data3x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 4 ? { Data4x0, Data4x1, Data4x2, Data4x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 5 ? { Data5x0, Data5x1, Data5x2, Data5x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 6 ? { Data6x0, Data6x1, Data6x2, Data6x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 7 ? { Data7x0, Data7x1, Data7x2, Data7x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 8 ? { Data8x0, Data8x1, Data8x2, Data8x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 9 ? { Data9x0, Data9x1, Data9x2, Data9x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 10 ? { Data10x0, Data10x1, Data10x2, Data10x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 11 ? { Data11x0, Data11x1, Data11x2, Data11x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 12 ? { Data12x0, Data12x1, Data12x2, Data12x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 13 ? { Data13x0, Data13x1, Data13x2, Data13x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 14 ? { Data14x0, Data14x1, Data14x2, Data14x3 } :
+	{Sel3, Sel2, Sel1, Sel0} == 15 ? { Data15x0, Data15x1, Data15x2, Data15x3 } : 'bx;
+endmodule
+
+module mux1_5_32(
+	Sel0, Sel1, Sel2, Sel3, Sel4,
+	Data0x0, Data1x0, Data2x0, Data3x0, Data4x0, Data5x0, Data6x0, Data7x0, Data8x0, Data9x0, Data10x0, Data11x0, Data12x0, Data13x0, Data14x0, Data15x0,
+	Data16x0, Data17x0, Data18x0, Data19x0, Data20x0, Data21x0, Data22x0, Data23x0, Data24x0, Data25x0, Data26x0, Data27x0, Data28x0, Data29x0, Data30x0, Data31x0,
+	Result0
+);
+input Sel0, Sel1, Sel2, Sel3, Sel4;
+input Data0x0, Data1x0, Data2x0, Data3x0, Data4x0, Data5x0, Data6x0, Data7x0, Data8x0, Data9x0, Data10x0, Data11x0, Data12x0, Data13x0, Data14x0, Data15x0;
+input Data16x0, Data17x0, Data18x0, Data19x0, Data20x0, Data21x0, Data22x0, Data23x0, Data24x0, Data25x0, Data26x0, Data27x0, Data28x0, Data29x0, Data30x0, Data31x0;
+output Result0;
+assign Result0 =
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 0 ? Data0x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 1 ? Data1x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 2 ? Data2x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 3 ? Data3x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 4 ? Data4x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 5 ? Data5x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 6 ? Data6x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 7 ? Data7x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 8 ? Data8x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 9 ? Data9x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 10 ? Data10x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 11 ? Data11x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 12 ? Data12x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 13 ? Data13x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 14 ? Data14x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 15 ? Data15x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 16 ? Data16x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 17 ? Data17x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 18 ? Data18x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 19 ? Data19x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 20 ? Data20x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 21 ? Data21x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 22 ? Data22x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 23 ? Data23x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 24 ? Data24x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 25 ? Data25x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 26 ? Data26x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 27 ? Data27x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 28 ? Data28x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 29 ? Data29x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 30 ? Data30x0 :
+	{Sel4, Sel3, Sel2, Sel1, Sel0} == 31 ? Data31x0 : 'bx;
+endmodule
+

manual/CHAPTER_StateOfTheArt/simlib_yosys.v

@@ -0,0 +1,166 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  ---
+ *
+ *  The internal logic cell simulation library.
+ *
+ *  This verilog library contains simple simulation models for the internal
+ *  logic cells (_INV_, _AND_, ...) that are generated by the default technology
+ *  mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
+ *
+ */
+
+module _INV_(A, Y);
+input A;
+output Y;
+assign Y = ~A;
+endmodule
+
+module _AND_(A, B, Y);
+input A, B;
+output Y;
+assign Y = A & B;
+endmodule
+
+module _OR_(A, B, Y);
+input A, B;
+output Y;
+assign Y = A | B;
+endmodule
+
+module _XOR_(A, B, Y);
+input A, B;
+output Y;
+assign Y = A ^ B;
+endmodule
+
+module _MUX_(A, B, S, Y);
+input A, B, S;
+output reg Y;
+always @* begin
+	if (S)
+		Y = B;
+	else
+		Y = A;
+end
+endmodule
+
+module _DFF_N_(D, Q, C);
+input D, C;
+output reg Q;
+always @(negedge C) begin
+	Q <= D;
+end
+endmodule
+
+module _DFF_P_(D, Q, C);
+input D, C;
+output reg Q;
+always @(posedge C) begin
+	Q <= D;
+end
+endmodule
+
+module _DFF_NN0_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+module _DFF_NN1_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+module _DFF_NP0_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(negedge C or posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+module _DFF_NP1_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(negedge C or posedge R) begin
+	if (R == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+module _DFF_PN0_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(posedge C or negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+module _DFF_PN1_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(posedge C or negedge R) begin
+	if (R == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+module _DFF_PP0_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+module _DFF_PP1_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+

manual/CHAPTER_StateOfTheArt/sis-1.3.6-buildfixes.patch

@@ -0,0 +1,113 @@
+Some minor build fixes for sis-1.3.6 as it can be downloaded from
+http://www-cad.eecs.berkeley.edu/~pchong/sis.html or
+http://embedded.eecs.berkeley.edu/Alumni/pchong/sis.html
+
+diff --git a/sis/io/read_kiss.c b/sis/io/read_kiss.c
+index 814e526..c862892 100644
+--- a/sis/io/read_kiss.c
++++ b/sis/io/read_kiss.c
+@@ -10,7 +10,6 @@
+ #ifdef SIS
+ #include "sis.h"
+ 
+-extern void read_error();
+ extern int read_lineno;
+ extern char *read_filename;
+ 
+diff --git a/sis/pld/act_bdd.c b/sis/pld/act_bdd.c
+index 4fb4415..a5cd74c 100644
+--- a/sis/pld/act_bdd.c
++++ b/sis/pld/act_bdd.c
+@@ -141,6 +141,8 @@ char *name;
+     return p_vertex;
+ }
+ 
++static int compare();
++
+ /* Or 2 ACT's*/
+ act_t *
+ my_or_act_F(array_b,cover, array)
+@@ -148,7 +150,6 @@ array_t *array_b;
+ array_t *array;
+ sm_row *cover;
+ {
+-    static int compare();
+     int  i;
+     act_t *up_vertex, *down_vertex, *vertex;
+     sm_element *p;
+diff --git a/sis/pld/act_ite.c b/sis/pld/act_ite.c
+index a35f2fb..7b824df 100644
+--- a/sis/pld/act_ite.c
++++ b/sis/pld/act_ite.c
+@@ -125,6 +125,8 @@ node_t *fanin;
+    and the minimum column cover variables in cover, generates an ite for the 
+    original function. */
+ 
++static int compare();
++
+ ite_vertex *
+ my_or_ite_F(array_b, cover, array, network)
+ array_t *array_b;
+@@ -132,7 +134,6 @@ array_t *array;
+ sm_row *cover;
+ network_t *network;
+ {
+-    static int compare();
+     int  i;
+     ite_vertex *vertex;
+     sm_element *p;
+diff --git a/sis/pld/xln_merge.c b/sis/pld/xln_merge.c
+index 075e6c5..16f4d61 100644
+--- a/sis/pld/xln_merge.c
++++ b/sis/pld/xln_merge.c
+@@ -284,6 +284,7 @@ array_t	        *match1_array, *match2_array;
+ 
+ }
+ 
++static sm_row *xln_merge_find_neighbor_of_row1_with_minimum_neighbors();
+ 
+ /*----------------------------------------------------------------------------------------------------
+   An alternate to lindo option. Uses greedy merging. A node with minimum mergeable nodes is picked
+@@ -296,7 +297,6 @@ xln_merge_nodes_without_lindo(coeff, cand_node_array, match1_array, match2_array
+ { 
+   node_t *n1, *n2;
+   sm_row *row1, *row2;
+-  static sm_row *xln_merge_find_neighbor_of_row1_with_minimum_neighbors();
+ 
+   while (TRUE) {
+       row1 = sm_shortest_row(coeff);
+diff --git a/sis/pld/xln_part_dec.c b/sis/pld/xln_part_dec.c
+index 1c856bd..b78828a 100644
+--- a/sis/pld/xln_part_dec.c
++++ b/sis/pld/xln_part_dec.c
+@@ -49,13 +49,14 @@ int size;
+ 
+ 
+ 
++static int kernel_value();
++
+ int
+ split_node(network, node, size) 
+ network_t *network;
+ node_t *node;
+ int size;
+ {
+-    static int kernel_value();
+     int i, value = 1;
+     kern_node *sorted;
+     divisor_t *div, *best_div;
+diff --git a/xsis/Makefile.am b/xsis/Makefile.am
+index 196d98b..686fdf4 100644
+--- a/xsis/Makefile.am
++++ b/xsis/Makefile.am
+@@ -1,8 +1,8 @@
+ xsis_SOURCES_local = NetPlot.c NetPlot.h NetPlotP.h main.c xastg.c \
+     xblif.c xcmd.c xhelp.c xsis.c xsis.h xutil.c \
+     blif50.px ghost.px help50.px sis50.px
+-AM_CPPFLAGS = -I../sis/include -I@SIS_X_INCLUDES@
+-AM_LDFLAGS = -L@SIS_X_LIBRARIES@
++AM_CPPFLAGS = -I../sis/include
++AM_LDFLAGS =
+ LDADD = ../sis/libsis.a -lXaw -lXmu -lXt -lXext -lX11 -lm
+ 
+ if SIS_COND_X

manual/CHAPTER_StateOfTheArt/synth.sh

@@ -0,0 +1,64 @@
+#!/bin/bash
+
+yosys_bin="/usr/local/synthesis/src/yosys/yosys"
+hana_bin="/usr/local/synthesis/src/hana/bin/hana"
+vl2mv_bin="/usr/local/synthesis/bin/vl2mv"
+vis_bin="/usr/local/synthesis/bin/vis"
+iverilog_bin="/usr/local/synthesis/bin/iverilog-0.8"
+odin_bin="/usr/local/synthesis/src/vtr_release/ODIN_II/odin_II.exe"
+abc_bin="/usr/local/synthesis/src/alanmi-abc-b5750272659f/abc"
+edif2ngd="/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/edif2ngd"
+netgen="/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/netgen"
+
+all_modes="yosys hana vis icarus odin"
+all_sources="always01 always02 always03 arrays01 forgen01 forgen02"
+
+if [ "$*" == "ALL" ]; then
+	for mode in $all_modes; do
+		for src in $all_sources; do
+			echo "synth.sh $mode $src.v ${src}_${mode}.v"
+			( set -x; bash synth.sh $mode $src.v ${src}_${mode}.v || rm -f ${src}_${mode}.v; ) > ${src}_${mode}.log 2>&1
+		done
+	done
+	exit
+fi
+
+mode="$1"
+source="$2"
+output="$3"
+prefix="${output%.v}"
+
+help() {
+	echo "$0 ALL" >&2
+	echo "$0 {yosys|hana|vis|icarus|odin} <source-file> <output-file>" >&2
+	exit 1
+}
+
+if [ "$#" != 3 -o ! -f "$source" ]; then
+	help
+fi
+
+set -ex
+
+case "$mode" in
+	yosys)
+		$yosys_bin -o $output -b "verilog -noattr" -p proc -p opt -p memory -p opt -p techmap -p opt $source ;;
+	hana)
+		$hana_bin -s $output $source ;;
+	vis)
+		$vl2mv_bin -o $prefix.mv $source
+		{ echo "read_blif_mv $prefix.mv"; echo "write_verilog $output"; } | $abc_bin ;;
+	icarus)
+		rm -f $prefix.ngo $prefix.v
+		$iverilog_bin -t fpga -o $prefix.edif $source
+		$edif2ngd $prefix.edif $prefix.ngo
+		$netgen -ofmt verilog $prefix.ngo $prefix.v
+		sed -re '/timescale/ s,^,//,;' -i $prefix.v ;;
+	odin)
+		$odin_bin -o $prefix.blif -V $source
+		sed -re 's,top\^,,g; s,clock,_clock,g;' -i $prefix.blif
+		{ echo "read_blif $prefix.blif"; echo "write_verilog $output"; } | $abc_bin ;;
+	*)
+		help
+esac
+

manual/CHAPTER_StateOfTheArt/validate_tb.sh

@@ -0,0 +1,55 @@
+#!/bin/bash
+
+set -ex
+
+yosys_bin="/usr/local/synthesis/src/yosys/yosys"
+iverilog_bin="iverilog"
+
+all_modes="yosys hana vis icarus odin"
+all_sources="always01 always02 always03 arrays01 forgen01 forgen02"
+
+gcc -o cmp_tbdata cmp_tbdata.c
+
+for src in $all_sources; do
+	echo; echo
+	$yosys_bin -o ${src}_tb.v -b autotest ${src}.v
+	$iverilog_bin -o ${src}_tb ${src}_tb.v ${src}.v
+	./${src}_tb > ${src}_tb.out
+        for mode in $all_modes; do
+		simlib=""
+		[ -f ${src}_${mode}.v ] || continue
+		[ -f simlib_${mode}.v ] && simlib="simlib_${mode}.v"
+		if $iverilog_bin -o ${src}_${mode}_tb -s testbench ${src}_tb.v ${src}_${mode}.v $simlib; then
+			./${src}_${mode}_tb > ${src}_${mode}_tb.out
+		else
+			rm -f ${src}_${mode}_tb.out
+		fi
+        done
+done
+
+set +x
+echo; echo; echo
+
+{
+	for mode in $all_modes; do
+		echo -en "\t$mode"
+	done; echo
+
+	for src in $all_sources; do
+		echo -n "$src"
+		for mode in $all_modes; do
+			if [ -f ${src}_${mode}.v ]; then
+				if [ ! -s ${src}_${mode}_tb.out ]; then
+					echo -en "\tmissing"
+				elif ./cmp_tbdata ${src}_tb.out ${src}_${mode}_tb.out; then
+					echo -en "\tok"
+				else
+					echo -en "\tfailed"
+				fi
+			else
+				echo -en "\terror"
+			fi
+		done; echo
+	done
+} | expand -t12
+