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Renamed manual/FILES_* directories

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This commit is contained in:
Clifford Wolf 2014-01-28 06:55:47 +01:00
parent 842ca2f011
commit 2cb47355d4
29 changed files with 9 additions and 9 deletions
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14
manual/CHAPTER_Eval/openmsp430.prj Normal file
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verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v"
verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v"