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peepopt: add formal only peepopt to rewrite latches to ffs in clock gates

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* this is gated behind the -formalclk flag, which also disables the other
  synthesis focused optimizations
This commit is contained in:
George Rennie 2024-08-06 16:32:26 +01:00
parent d08bf671b2
commit 2cb3b6e9b8
3 changed files with 81 additions and 5 deletions
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26
passes/pmgen/peepopt.cc
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@ -40,7 +40,7 @@ struct PeepoptPass : public Pass {
log("\n");
log("This pass applies a collection of peephole optimizers to the current design.\n");
log("\n");
log("This pass employs the following rules:\n");
log("This pass employs the following rules by default:\n");
log("\n");
log(" * muldiv - Replace (A*B)/B with A\n");
log("\n");
@ -57,14 +57,26 @@ struct PeepoptPass : public Pass {
log(" limits the amount of padding to a multiple of the data, \n");
log(" to avoid high resource usage from large temporary MUX trees.\n");
log("\n");
log("If -formalclk is specified it instead employs the following rules:\n");
log("\n");
log(" * clockgateff - Replace latch based clock gating patterns with a flip-flop\n");
log(" based pattern to prevent combinational paths from the\n");
log(" output to the enable input after running clk2fflogic.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n");
bool formalclk = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-formalclk") {
formalclk = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -86,10 +98,14 @@ struct PeepoptPass : public Pass {
pm.setup(module->selected_cells());
pm.run_shiftadd();
pm.run_shiftmul_right();
pm.run_shiftmul_left();
pm.run_muldiv();
if (formalclk) {
pm.run_formal_clockgateff();
} else {
pm.run_shiftadd();
pm.run_shiftmul_right();
pm.run_shiftmul_left();
pm.run_muldiv();
}
}
}
}