mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-11 05:30:53 +00:00
Added spice testbench to techlibs/cmos
This commit is contained in:
parent
bbe5aa446b
commit
2c9bd23801
5 changed files with 73 additions and 6 deletions
|
@ -1,12 +1,12 @@
|
|||
module counter (clk, rst, en, count);
|
||||
|
||||
input clk, rst, en;
|
||||
output reg [3:0] count;
|
||||
output reg [2:0] count;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst)
|
||||
count <= 4'd0;
|
||||
count <= 3'd0;
|
||||
else if (en)
|
||||
count <= count + 4'd1;
|
||||
count <= count + 3'd1;
|
||||
|
||||
endmodule
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue