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Merge pull request #1778 from rswarbrick/sv-defines

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Add support for SystemVerilog-style `define to Verilog frontend
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N. Engelhardt 2020-03-30 13:51:12 +02:00 • committed by GitHub
commit 2c847e7efe
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11 changed files with 636 additions and 151 deletions
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passes/cmds/design.cc
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@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
#include "frontends/verilog/preproc.h"
#include "frontends/ast/ast.h"
YOSYS_NAMESPACE_BEGIN
@ -346,7 +347,7 @@ struct DesignPass : public Pass {
delete node;
design->verilog_globals.clear();
design->verilog_defines.clear();
design->verilog_defines->clear();
}
if (!load_name.empty() || pop_mode)