Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

passes/hierarchy/submod.cc

@@ -33,7 +33,7 @@ struct SubmodWorker
 	CellTypes ct;
 	RTLIL::Design *design;
 	RTLIL::Module *module;
-	pool<Wire*> outputs;
+	pool<Wire*> constants, outputs;
 
 	bool copy_mode;
 	std::string opt_name;
@@ -125,7 +125,7 @@ struct SubmodWorker
 			RTLIL::Wire *wire = it.first;
 			wire_flags_t &flags = it.second;
 
-			if (wire->port_input)
+			if (wire->port_input || constants.count(wire))
 				flags.is_ext_driven = true;
 			if (wire->port_output || outputs.count(wire))
 				flags.is_ext_used = true;
@@ -235,6 +235,14 @@ struct SubmodWorker
 				outputs.insert(c.wire);
 			}
 		}
+		for (auto wire : module->wires()) {
+			auto sig = sigmap(wire);
+			for (auto c : sig.chunks()) {
+				if (c.wire)
+					continue;
+				constants.insert(wire);
+			}
+		}
 
 		if (opt_name.empty())
 		{

tests/various/submod.ys

@@ -23,3 +23,31 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+
+design -reset
+read_verilog <<EOT
+module top(input a, output [1:0] b);
+(* submod="bar" *) sub s1(a, b[1]);
+assign b[0] = 1'b0;
+endmodule
+
+module sub(input a, output c);
+assign c = a;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+design -save gold
+
+submod
+dump
+flatten
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter