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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

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This commit is contained in:
Eddie Hung 2019-11-22 17:24:45 -08:00
commit 2c5dfd802d
2 changed files with 38 additions and 2 deletions
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12
passes/hierarchy/submod.cc
View file

@ -33,7 +33,7 @@ struct SubmodWorker
CellTypes ct; CellTypes ct;
RTLIL::Design *design; RTLIL::Design *design;
RTLIL::Module *module; RTLIL::Module *module;
pool<Wire*> outputs; pool<Wire*> constants, outputs;
bool copy_mode; bool copy_mode;
std::string opt_name; std::string opt_name;
@ -125,7 +125,7 @@ struct SubmodWorker
RTLIL::Wire *wire = it.first; RTLIL::Wire *wire = it.first;
wire_flags_t &flags = it.second; wire_flags_t &flags = it.second;
if (wire->port_input) if (wire->port_input || constants.count(wire))
flags.is_ext_driven = true; flags.is_ext_driven = true;
if (wire->port_output || outputs.count(wire)) if (wire->port_output || outputs.count(wire))
flags.is_ext_used = true; flags.is_ext_used = true;
@ -235,6 +235,14 @@ struct SubmodWorker
outputs.insert(c.wire); outputs.insert(c.wire);
} }
} }
for (auto wire : module->wires()) {
auto sig = sigmap(wire);
for (auto c : sig.chunks()) {
if (c.wire)
continue;
constants.insert(wire);
}
}
if (opt_name.empty()) if (opt_name.empty())
{ {

28
tests/various/submod.ys
View file

@ -23,3 +23,31 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog <<EOT
module top(input a, output [1:0] b);
(* submod="bar" *) sub s1(a, b[1]);
assign b[0] = 1'b0;
endmodule
module sub(input a, output c);
assign c = a;
endmodule
EOT
hierarchy -top top
proc
design -save gold
submod
dump
flatten
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter