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Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
This commit is contained in:
Eddie Hung
parent
162eab6b74
commit
2c0be7aa5d
6 changed files with 119 additions and 40 deletions
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@ -2,18 +2,27 @@ pattern ice40_dsp
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state <SigBit> clock
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state <bool> clock_pol
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state <SigSpec> sigA sigB sigCD sigH sigO
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state <SigSpec> sigA sigB sigCD sigH sigO sigOused
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state <Cell*> addAB muxAB
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match mul
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select mul->type.in($mul, $__MUL16X16)
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select mul->type.in($mul, \SB_MAC16)
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select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
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select GetSize(mul->getPort(\Y)) > 10
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endmatch
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code sigH
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if (mul->type == $mul)
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sigH = mul->getPort(\Y);
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else if (mul->type == \SB_MAC16)
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sigH = mul->getPort(\O);
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else log_abort();
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if (GetSize(sigH) <= 10)
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reject;
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endcode
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match ffA
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// TODO: Support $dffe too by checking if all enable signals are identical
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select ffA->type.in($dff)
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filter mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
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filter !port(mul, \A).remove_const().empty()
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filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
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optional
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@ -23,9 +32,9 @@ code sigA clock clock_pol
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sigA = port(mul, \A);
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if (ffA) {
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for (auto b : port(ffA, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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for (auto b : port(ffA, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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clock = port(ffA, \CLK).as_bit();
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clock_pol = param(ffA, \CLK_POLARITY).as_bool();
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@ -36,6 +45,7 @@ endcode
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match ffB
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select ffB->type.in($dff)
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filter mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
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filter !port(mul, \B).remove_const().empty()
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filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
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optional
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@ -45,9 +55,9 @@ code sigB clock clock_pol
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sigB = port(mul, \B);
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if (ffB) {
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for (auto b : port(ffB, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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for (auto b : port(ffB, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffB, \CLK).as_bit();
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bool cp = param(ffB, \CLK_POLARITY).as_bool();
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@ -65,19 +75,20 @@ endcode
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match ffH
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select ffH->type.in($dff)
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select nusers(port(ffH, \D)) == 2
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index <SigSpec> port(ffH, \D) === port(mul, \Y)
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index <SigSpec> port(ffH, \D) === sigH
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// Ensure pipeline register is not already used
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filter mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
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optional
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endmatch
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code sigH sigO clock clock_pol
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sigH = port(mul, \Y);
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sigO = sigH;
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if (ffH) {
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sigH = port(ffH, \Q);
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for (auto b : sigH)
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if (b.wire->get_bool_attribute(\keep))
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reject;
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for (auto b : sigH)
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if (b.wire->get_bool_attribute(\keep))
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reject;
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sigO = sigH;
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@ -119,6 +130,13 @@ code addAB sigCD sigO
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sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
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}
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if (addAB) {
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if (mul->type == \SB_MAC16) {
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// Ensure that adder is not used
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if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
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param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
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reject;
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}
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int natural_mul_width = GetSize(sigA) + GetSize(sigB);
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int actual_mul_width = GetSize(sigH);
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int actual_acc_width = GetSize(sigO);
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@ -154,28 +172,49 @@ code muxAB
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muxAB = muxB;
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endcode
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// Extract the bits of P that actually have a consumer
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// (as opposed to being a dummy)
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code sigOused
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for (int i = 0; i < GetSize(sigO); i++)
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if (!sigO[i].wire || nusers(sigO[i]) == 1)
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sigOused.append(State::Sx);
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else
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sigOused.append(sigO[i]);
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endcode
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match ffO_lo
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select ffO_lo->type.in($dff)
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filter GetSize(sigO) >= param(ffO_lo, \WIDTH).as_int()
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filter nusers(sigO.extract(0,param(ffO_lo, \WIDTH).as_int())) == 2
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filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,param(ffO_lo, \WIDTH).as_int()).to_sigbit_set())
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filter nusers(sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()))) == 2
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filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set())
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optional
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endmatch
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match ffO_hi
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select ffO_hi->type.in($dff)
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filter GetSize(sigO) >= 16+param(ffO_hi, \WIDTH).as_int()
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filter nusers(sigO.extract(16,param(ffO_hi, \WIDTH).as_int())) == 2
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filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,param(ffO_hi, \WIDTH).as_int()).to_sigbit_set())
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filter GetSize(sigOused) > 16
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filter nusers(sigOused.extract_end(16)) == 2
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filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set())
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optional
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endmatch
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code clock clock_pol sigO sigCD
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if (ffO_lo || ffO_hi) {
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if (mul->type == \SB_MAC16) {
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// Ensure that register is not already used
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if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
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param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
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reject;
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// Ensure that OLOADTOP/OLOADBOT is unused or zero
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if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
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|| (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
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reject;
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}
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if (ffO_lo) {
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for (auto b : port(ffO_lo, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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for (auto b : port(ffO_lo, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffO_lo, \CLK).as_bit();
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bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
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@ -186,14 +225,13 @@ code clock clock_pol sigO sigCD
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clock = c;
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clock_pol = cp;
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if (port(ffO_lo, \Q) != sigO.extract(0,param(ffO_lo, \WIDTH).as_int()))
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sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
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sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
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}
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if (ffO_hi) {
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for (auto b : port(ffO_hi, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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for (auto b : port(ffO_hi, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffO_hi, \CLK).as_bit();
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bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
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@ -204,8 +242,7 @@ code clock clock_pol sigO sigCD
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clock = c;
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clock_pol = cp;
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if (port(ffO_hi, \Q) != sigO.extract(16,param(ffO_hi, \WIDTH).as_int()))
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sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
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sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
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}
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// Loading value into output register is not
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