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design: fix signorm commit connectivity to design

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This commit is contained in:
Emil J. Tywoniak 2026-03-18 00:44:20 +01:00
parent 05fdff65f0
commit 2c024d5e74
1 changed files with 4 additions and 1 deletions
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5
passes/cmds/design.cc
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@ -338,8 +338,11 @@ struct DesignPass : public Pass {
{ {
RTLIL::Design *design_copy = new RTLIL::Design; RTLIL::Design *design_copy = new RTLIL::Design;
for (auto mod : design->modules()) for (auto mod : design->modules()) {
// Triggers signorm flush if needed (hacky)
(void)mod->connections();
design_copy->add(mod->clone()); design_copy->add(mod->clone());
}
design_copy->selection_stack = design->selection_stack; design_copy->selection_stack = design->selection_stack;
design_copy->selection_vars = design->selection_vars; design_copy->selection_vars = design->selection_vars;