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Use only module->addCell() and module->remove() to create and delete cells

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This commit is contained in:
Clifford Wolf 2014-07-25 15:05:18 +02:00
parent 5826670009
commit 2bec47a404
35 changed files with 259 additions and 582 deletions
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5
passes/sat/freduce.cc
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@ -718,12 +718,9 @@ struct FreduceWorker
{
inv_sig = module->addWire(NEW_ID);
RTLIL::Cell *inv_cell = new RTLIL::Cell;
inv_cell->name = NEW_ID;
inv_cell->type = "$_INV_";
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
inv_cell->connections["\\A"] = grp[0].bit;
inv_cell->connections["\\Y"] = inv_sig;
module->add(inv_cell);
}
module->connections.push_back(RTLIL::SigSig(grp[i].bit, inv_sig));