Use only module->addCell() and module->remove() to create and delete cells

passes/opt/opt_clean.cc

@@ -90,9 +90,8 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 		if (verbose)
 			log("  removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
 		OPT_DID_SOMETHING = true;
-		module->cells.erase(cell->name);
+		module->remove(cell);
 		count_rm_cells++;
-		delete cell;
 	}
 }
 

passes/opt/opt_const.cc

@@ -81,8 +81,7 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i
 			module->name.c_str(), log_signal(Y), log_signal(out_val));
 	// ILANG_BACKEND::dump_cell(stderr, "--> ", cell);
 	module->connections.push_back(RTLIL::SigSig(Y, out_val));
-	module->cells.erase(cell->name);
-	delete cell;
+	module->remove(cell);
 	OPT_DID_SOMETHING = true;
 	did_something = true;
 }

passes/opt/opt_muxtree.cc

@@ -190,8 +190,7 @@ struct OptMuxtreeWorker
 				continue;
 
 			if (live_ports.size() == 0) {
-				module->cells.erase(mi.cell->name);
-				delete mi.cell;
+				module->remove(mi.cell);
 				continue;
 			}
 
@@ -207,8 +206,7 @@ struct OptMuxtreeWorker
 			{
 				RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size());
 				module->connections.push_back(RTLIL::SigSig(sig_y, sig_in));
-				module->cells.erase(mi.cell->name);
-				delete mi.cell;
+				module->remove(mi.cell);
 			}
 			else
 			{

passes/opt/opt_reduce.cc

@@ -124,19 +124,13 @@ struct OptReduceWorker
 
 			if (this_s.size() > 1)
 			{
-				RTLIL::Wire *reduce_or_wire = new RTLIL::Wire;
-				reduce_or_wire->name = NEW_ID;
-				module->wires[reduce_or_wire->name] = reduce_or_wire;
-
-				RTLIL::Cell *reduce_or_cell = new RTLIL::Cell;
-				reduce_or_cell->name = NEW_ID;
-				reduce_or_cell->type = "$reduce_or";
+				RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
 				reduce_or_cell->connections["\\A"] = this_s;
 				reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 				reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
 				reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-				module->cells[reduce_or_cell->name] = reduce_or_cell;
 
+				RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
 				this_s = RTLIL::SigSpec(reduce_or_wire);
 				reduce_or_cell->connections["\\Y"] = this_s;
 			}
@@ -157,8 +151,7 @@ struct OptReduceWorker
 		{
 			module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"]));
 			assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]);
-			module->cells.erase(cell->name);
-			delete cell;
+			module->remove(cell);
 		}
 		else
 		{

passes/opt/opt_rmdff.cc

@@ -143,8 +143,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 delete_dff:
 	log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str());
 	OPT_DID_SOMETHING = true;
-	mod->cells.erase(dff->name);
-	delete dff;
+	mod->remove(dff);
 	return true;
 }
 

passes/opt/opt_share.cc

@@ -271,10 +271,9 @@ struct OptShareWorker
 						}
 					}
 					log("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
-					module->cells.erase(cell->name);
+					module->remove(cell);
 					OPT_DID_SOMETHING = true;
 					total_count++;
-					delete cell;
 				} else {
 					sharemap[cell] = cell;
 				}