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Use only module->addCell() and module->remove() to create and delete cells

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This commit is contained in:
Clifford Wolf 2014-07-25 15:05:18 +02:00
parent 5826670009
commit 2bec47a404
35 changed files with 259 additions and 582 deletions
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18
passes/memory/memory_collect.cc
View file

@ -58,7 +58,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
RTLIL::SigSpec sig_rd_addr;
RTLIL::SigSpec sig_rd_data;
std::vector<std::string> del_cell_ids;
std::vector<RTLIL::Cell*> del_cells;
std::vector<RTLIL::Cell*> memcells;
for (auto &cell_it : module->cells) {
@ -74,7 +74,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
{
wr_ports++;
del_cell_ids.push_back(cell->name);
del_cells.push_back(cell);
RTLIL::SigSpec clk = cell->connections["\\CLK"];
RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
@ -101,7 +101,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name)
{
rd_ports++;
del_cell_ids.push_back(cell->name);
del_cells.push_back(cell);
RTLIL::SigSpec clk = cell->connections["\\CLK"];
RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
@ -129,10 +129,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
std::stringstream sstr;
sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++);
RTLIL::Cell *mem = new RTLIL::Cell;
mem->name = sstr.str();
mem->type = "$mem";
RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
mem->parameters["\\MEMID"] = RTLIL::Const(memory->name);
mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width);
mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset);
@ -170,11 +167,8 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->connections["\\RD_ADDR"] = sig_rd_addr;
mem->connections["\\RD_DATA"] = sig_rd_data;
for (auto &id : del_cell_ids) {
delete module->cells[id];
module->cells.erase(id);
}
module->cells[mem->name] = mem;
for (auto c : del_cells)
module->remove(c);
}
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)

42
passes/memory/memory_map.cc
View file

@ -57,8 +57,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
// delete unused memory cell
if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) {
module->cells.erase(cell->name);
delete cell;
module->remove(cell);
return;
}
@ -117,9 +116,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
}
else
{
RTLIL::Cell *c = new RTLIL::Cell;
c->name = genid(cell->name, "", i);
c->type = "$dff";
RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
if (clocks_pol.bits.size() > 0) {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
@ -128,7 +125,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0);
}
module->cells[c->name] = c;
RTLIL::Wire *w_in = new RTLIL::Wire;
w_in->name = genid(cell->name, "", i, "$d");
@ -164,14 +160,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
{
if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1)
{
RTLIL::Cell *c = new RTLIL::Cell;
c->name = genid(cell->name, "$rdreg", i);
c->type = "$dff";
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
c->connections["\\D"] = rd_addr;
module->cells[c->name] = c;
count_dff++;
RTLIL::Wire *w = new RTLIL::Wire;
@ -184,14 +177,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
}
else
{
RTLIL::Cell *c = new RTLIL::Cell;
c->name = genid(cell->name, "$rdreg", i);
c->type = "$dff";
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
c->connections["\\Q"] = rd_signals.back();
module->cells[c->name] = c;
count_dff++;
RTLIL::Wire *w = new RTLIL::Wire;
@ -211,13 +201,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
for (size_t k = 0; k < rd_signals.size(); k++)
{
RTLIL::Cell *c = new RTLIL::Cell;
c->name = genid(cell->name, "$rdmux", i, "", j, "", k);
c->type = "$mux";
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
c->connections["\\Y"] = rd_signals[k];
c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1);
module->cells[c->name] = c;
count_mux++;
RTLIL::Wire *w = new RTLIL::Wire;
@ -258,9 +245,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width);
RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width);
RTLIL::Cell *c = new RTLIL::Cell;
c->name = genid(cell->name, "$wreq", i, "", j);
c->type = "$eq";
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq");
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"];
@ -268,7 +253,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits);
c->connections["\\B"] = wr_addr;
module->cells[c->name] = c;
count_wrmux++;
RTLIL::Wire *w_seladdr = new RTLIL::Wire;
@ -293,9 +277,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
if (wr_bit != RTLIL::SigSpec(1, 1))
{
c = new RTLIL::Cell;
c->name = genid(cell->name, "$wren", i, "", j, "", wr_offset);
c->type = "$and";
c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and");
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
@ -303,7 +285,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
c->connections["\\A"] = w;
c->connections["\\B"] = wr_bit;
module->cells[c->name] = c;
w = new RTLIL::Wire;
w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y");
@ -311,14 +292,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->connections["\\Y"] = RTLIL::SigSpec(w);
}
c = new RTLIL::Cell;
c->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset);
c->type = "$mux";
c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
c->parameters["\\WIDTH"] = wr_width;
c->connections["\\A"] = sig.extract(wr_offset, wr_width);
c->connections["\\B"] = wr_data.extract(wr_offset, wr_width);
c->connections["\\S"] = RTLIL::SigSpec(w);
module->cells[c->name] = c;
w = new RTLIL::Wire;
w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y");
@ -336,9 +314,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux);
module->cells.erase(cell->name);
delete cell;
return;
module->remove(cell);
}
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)

6
passes/memory/memory_share.cc
View file

@ -446,8 +446,7 @@ struct MemoryShareWorker
cell->connections.at("\\EN") = merged_en;
cell->connections.at("\\DATA") = merged_data;
module->cells.erase(wr_ports[last_i]->name);
delete wr_ports[last_i];
module->remove(wr_ports[last_i]);
wr_ports[last_i] = NULL;
log(" Active bits: ");
@ -617,8 +616,7 @@ struct MemoryShareWorker
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
wr_ports[i]->connections.at("\\EN") = en;
module->cells.erase(wr_ports[i-1]->name);
delete wr_ports[i-1];
module->remove(wr_ports[i-1]);
wr_ports[i-1] = NULL;
}

13
passes/memory/memory_unpack.cc
View file

@ -47,9 +47,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
for (int i = 0; i < num_rd_ports; i++)
{
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$memrd";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd");
cell->parameters["\\MEMID"] = mem_name;
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
@ -59,14 +57,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1);
cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits);
cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width);
module->add(cell);
}
for (int i = 0; i < num_wr_ports; i++)
{
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$memwr";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr");
cell->parameters["\\MEMID"] = mem_name;
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
@ -77,11 +72,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width);
cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits);
cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width);
module->add(cell);
}
module->cells.erase(memory->name);
delete memory;
module->remove(memory);
}
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)