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Use only module->addCell() and module->remove() to create and delete cells

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This commit is contained in:
Clifford Wolf 2014-07-25 15:05:18 +02:00
parent 5826670009
commit 2bec47a404
35 changed files with 259 additions and 582 deletions
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9
passes/cmds/delete.cc
View file

@ -107,7 +107,7 @@ struct DeletePass : public Pass {
}
std::set<std::string> delete_wires;
std::set<std::string> delete_cells;
std::set<RTLIL::Cell*> delete_cells;
std::set<std::string> delete_procs;
std::set<std::string> delete_mems;
@ -121,10 +121,10 @@ struct DeletePass : public Pass {
for (auto &it : module->cells) {
if (design->selected(module, it.second))
delete_cells.insert(it.first);
delete_cells.insert(it.second);
if ((it.second->type == "$memrd" || it.second->type == "$memwr") &&
delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
delete_cells.insert(it.first);
delete_cells.insert(it.second);
}
for (auto &it : module->processes)
@ -147,8 +147,7 @@ struct DeletePass : public Pass {
}
for (auto &it : delete_cells) {
delete module->cells.at(it);
module->cells.erase(it);
module->remove(it);
}
for (auto &it : delete_procs) {

10
passes/cmds/splice.cc
View file

@ -70,16 +70,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$slice";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice");
cell->parameters["\\OFFSET"] = offset;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig.size();
cell->connections["\\A"] = sig_a;
cell->connections["\\Y"] = module->addWire(NEW_ID, sig.size());
new_sig = cell->connections["\\Y"];
module->add(cell);
}
sliced_signals_cache[sig] = new_sig;
@ -130,16 +127,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$concat";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
cell->parameters["\\A_WIDTH"] = new_sig.size();
cell->parameters["\\B_WIDTH"] = sig2.size();
cell->connections["\\A"] = new_sig;
cell->connections["\\B"] = sig2;
cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size());
new_sig = cell->connections["\\Y"];
module->add(cell);
}
spliced_signals_cache[sig] = new_sig;