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Use only module->addCell() and module->remove() to create and delete cells

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This commit is contained in:
Clifford Wolf 2014-07-25 15:05:18 +02:00
parent 5826670009
commit 2bec47a404
35 changed files with 259 additions and 582 deletions
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37
kernel/rtlil.cc
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@ -782,8 +782,14 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
for (auto &it : memories)
new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
for (auto &it : cells)
new_mod->cells[it.first] = new RTLIL::Cell(*it.second);
for (auto &it : cells) {
new_mod->cells[it.first] = new RTLIL::Cell;
new_mod->cells[it.first]->name = it.second->name;
new_mod->cells[it.first]->type = it.second->type;
new_mod->cells[it.first]->connections = it.second->connections;
new_mod->cells[it.first]->parameters = it.second->parameters;
new_mod->cells[it.first]->attributes = it.second->attributes;
}
for (auto &it : processes)
new_mod->processes[it.first] = it.second->clone();
@ -834,6 +840,33 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
delete cell;
}
void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
{
assert(wires[wire->name] == wire);
wires.erase(wire->name);
wire->name = new_name;
add(wire);
}
void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
{
assert(cells[cell->name] == cell);
cells.erase(cell->name);
cell->name = new_name;
add(cell);
}
void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
{
assert(count_id(old_name) != 0);
if (wires.count(old_name))
rename(wires.at(old_name), new_name);
else if (cells.count(old_name))
rename(cells.at(old_name), new_name);
else
log_abort();
}
static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
{
if (a->port_id && !b->port_id)