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	intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
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					 2 changed files with 2 additions and 47 deletions
				
			
		|  | @ -1,21 +1,3 @@ | ||||||
| `ifdef cyclonev |  | ||||||
| `define SYNCPATH 262 |  | ||||||
| `define SYNCSETUP 522 |  | ||||||
| `define COMBPATH 0 |  | ||||||
| `endif |  | ||||||
| `ifdef cyclone10gx |  | ||||||
| `define SYNCPATH 219 |  | ||||||
| `define SYNCSETUP 268 |  | ||||||
| `define COMBPATH 0 |  | ||||||
| `endif |  | ||||||
| 
 |  | ||||||
| // fallback for when a family isn't detected (e.g. when techmapping for equivalence)
 |  | ||||||
| `ifndef SYNCPATH |  | ||||||
| `define SYNCPATH 0 |  | ||||||
| `define SYNCSETUP 0 |  | ||||||
| `define COMBPATH 0 |  | ||||||
| `endif |  | ||||||
| 
 |  | ||||||
| // This is a purely-synchronous flop, that ABC9 can use for sequential synthesis.
 | // This is a purely-synchronous flop, that ABC9 can use for sequential synthesis.
 | ||||||
| (* abc9_flop, lib_whitebox *) | (* abc9_flop, lib_whitebox *) | ||||||
| module $__MISTRAL_FF_SYNCONLY ( | module $__MISTRAL_FF_SYNCONLY ( | ||||||
|  | @ -23,33 +5,6 @@ module $__MISTRAL_FF_SYNCONLY ( | ||||||
|     output reg Q |     output reg Q | ||||||
| ); | ); | ||||||
| 
 | 
 | ||||||
| specify | MISTRAL_FF ff (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .ACLR(1'b1), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q)); | ||||||
|     if (ENA) (posedge CLK => (Q : DATAIN)) = `SYNCPATH; |  | ||||||
|     if (ENA) (posedge CLK => (Q : SCLR)) = `SYNCPATH; |  | ||||||
|     if (ENA) (posedge CLK => (Q : SLOAD)) = `SYNCPATH; |  | ||||||
|     if (ENA) (posedge CLK => (Q : SDATA)) = `SYNCPATH; |  | ||||||
| 
 |  | ||||||
|     $setup(DATAIN, posedge CLK, `SYNCSETUP); |  | ||||||
|     $setup(ENA, posedge CLK, `SYNCSETUP); |  | ||||||
|     $setup(SCLR, posedge CLK, `SYNCSETUP); |  | ||||||
|     $setup(SLOAD, posedge CLK, `SYNCSETUP); |  | ||||||
|     $setup(SDATA, posedge CLK, `SYNCSETUP); |  | ||||||
| endspecify |  | ||||||
| 
 |  | ||||||
| initial begin |  | ||||||
|     // Altera flops initialise to zero.
 |  | ||||||
| 	Q = 0; |  | ||||||
| end |  | ||||||
| 
 |  | ||||||
| always @(posedge CLK) begin |  | ||||||
|     // Clock-enable
 |  | ||||||
| 	if (ENA) begin |  | ||||||
|         // Synchronous clear
 |  | ||||||
|         if (SCLR) Q <= 0; |  | ||||||
|         // Synchronous load
 |  | ||||||
|         else if (SLOAD) Q <= SDATA; |  | ||||||
|         else Q <= DATAIN; |  | ||||||
|     end |  | ||||||
| end |  | ||||||
| 
 | 
 | ||||||
| endmodule | endmodule | ||||||
|  |  | ||||||
|  | @ -90,7 +90,7 @@ specify | ||||||
|     $setup(SLOAD, posedge CLK, `SYNCSETUP); |     $setup(SLOAD, posedge CLK, `SYNCSETUP); | ||||||
|     $setup(SDATA, posedge CLK, `SYNCSETUP); |     $setup(SDATA, posedge CLK, `SYNCSETUP); | ||||||
| 
 | 
 | ||||||
|     (ACLR => Q) = `COMBPATH; |     if (!ACLR) (ACLR => Q) = `COMBPATH; | ||||||
| endspecify | endspecify | ||||||
| 
 | 
 | ||||||
| initial begin | initial begin | ||||||
|  |  | ||||||
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