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Merge branch 'main' of github.com:silimate/yosys into sim

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This commit is contained in:
Stan Lee 2026-03-02 14:34:52 -08:00
commit 2bb46d0453
12 changed files with 2274 additions and 19 deletions
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1
passes/silimate/Makefile.inc
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@ -13,6 +13,7 @@ OBJS += passes/silimate/reg_rename.o
OBJS += passes/silimate/splitfanout.o
OBJS += passes/silimate/splitlarge.o
OBJS += passes/silimate/splitnetlist.o
OBJS += passes/silimate/opt_timing_balance.o
OBJS += passes/silimate/opt_expand.o
GENFILES += passes/silimate/peepopt_expand.h

18
passes/silimate/negopt.cc
View file

@ -81,33 +81,47 @@ struct NegoptPass : public Pass {
run_post = true;
}
constexpr int max_iterations = 100;
for (auto module : design->selected_modules()) {
if (run_pre) {
did_something = true;
while (did_something) {
for (int iter = 0; iter < max_iterations && did_something; iter++) {
did_something = false;
peepopt_pm pm(module);
pm.setup(module->selected_cells());
pm.run_manual2sub(); // Reduce manual 2's complement to subtraction first
log_flush();
pm.run_sub2neg();
log_flush();
pm.run_negexpand();
log_flush();
pm.run_negneg();
log_flush();
pm.run_negmux();
log_flush();
}
if (did_something)
log_warning("NEGOPT pre reached max iterations (%d) in module %s without convergence.\n", max_iterations, log_id(module));
}
if (run_post) {
did_something = true;
while (did_something) {
for (int iter = 0; iter < max_iterations && did_something; iter++) {
did_something = false;
peepopt_pm pm(module);
pm.setup(module->selected_cells());
pm.run_negrebuild();
log_flush();
pm.run_muxneg();
log_flush();
pm.run_neg2sub();
log_flush();
}
if (did_something)
log_warning("NEGOPT post reached max iterations (%d) in module %s without convergence.\n", max_iterations, log_id(module));
}
}
}

1466
passes/silimate/opt_timing_balance.cc Normal file
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File diff suppressed because it is too large Load diff

5
passes/techmap/abc.cc
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@ -188,8 +188,11 @@ struct AbcProcess
~AbcProcess() {
if (pid == 0)
return;
if (to_child_pipe >= 0)
if (to_child_pipe >= 0) {
static const char quit_cmd[] = "quit\n";
if (write(to_child_pipe, quit_cmd, sizeof(quit_cmd) - 1)) {}
close(to_child_pipe);
}
int status;
int ret = waitpid(pid, &status, 0);
if (ret != pid) {

52
passes/techmap/aigmap.cc
View file

@ -72,16 +72,46 @@ struct AigmapPass : public Pass {
dict<IdString, int> stat_not_replaced;
int orig_num_cells = GetSize(module->cells());
dict<std::string, Aig> aig_cache;
pool<IdString> new_sel;
for (auto cell : module->selected_cells())
{
Aig aig(cell);
if (cell->type.in(ID($_AND_), ID($_NOT_))) {
not_replaced_count++;
stat_not_replaced[cell->type]++;
if (select_mode)
new_sel.insert(cell->name);
continue;
}
if (cell->type.in(ID($_AND_), ID($_NOT_)))
aig.name.clear();
if (nand_mode && cell->type == ID($_NAND_)) {
not_replaced_count++;
stat_not_replaced[cell->type]++;
if (select_mode)
new_sel.insert(cell->name);
continue;
}
if (nand_mode && cell->type == ID($_NAND_))
aig.name.clear();
if (cell->type[0] != '$') {
not_replaced_count++;
stat_not_replaced[cell->type]++;
if (select_mode)
new_sel.insert(cell->name);
continue;
}
std::string cache_key = cell->type.str();
cell->parameters.sort();
for (auto &p : cell->parameters)
cache_key += stringf(":%s=%s", p.first.c_str(), p.second.as_string().c_str());
auto cache_it = aig_cache.find(cache_key);
if (cache_it == aig_cache.end()) {
auto r = aig_cache.insert(std::make_pair(cache_key, Aig(cell)));
cache_it = r.first;
}
const Aig &aig = cache_it->second;
if (aig.name.empty()) {
not_replaced_count++;
@ -110,8 +140,8 @@ struct AigmapPass : public Pass {
if (nand_mode && node.inverter) {
bit = module->addWire(NEW_ID2_SUFFIX("bit"));
auto gate = module->addNandGate(NEW_ID2_SUFFIX("nand"), A, B, bit);
for (auto attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
for (const auto &attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
if (select_mode)
new_sel.insert(gate->name);
@ -123,8 +153,8 @@ struct AigmapPass : public Pass {
else {
bit = module->addWire(NEW_ID2_SUFFIX("bit"));
auto gate = module->addAndGate(NEW_ID2_SUFFIX("and"), A, B, bit);
for (auto attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
for (const auto &attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
if (select_mode)
new_sel.insert(gate->name);
}
@ -134,8 +164,8 @@ struct AigmapPass : public Pass {
if (node.inverter) {
SigBit new_bit = module->addWire(NEW_ID2_SUFFIX("new_bit"));
auto gate = module->addNotGate(NEW_ID2_SUFFIX("inv"), bit, new_bit);
for (auto attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
for (const auto &attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
bit = new_bit;
if (select_mode)
new_sel.insert(gate->name);